# DAC8740HRGET

**Texas Instruments** · Interface - Specialized · TQFN-24-EP(4x4)

DAC8740HRGET from Texas Instruments, in a TQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | XEN | input | Logic low enables the crystal oscillator (external crystal required), logic high disables it and selects an external CMOS clock or the internal oscillator; no digital input pin should be left floating. |
| 2 | CLKO | output | Clock output that can be configured when using the internal oscillator or an external crystal. |
| 3 | CLK_CFG0 | input | Configures the input/output clocking scheme together with XEN and CLK_CFG1; must not be left floating. |
| 4 | CLK_CFG1 | input | Configures the input/output clocking scheme together with XEN and CLK_CFG0; must not be left floating. |
| 5 | RST | input | Logic low resets the device and places it in power-down mode; logic high returns it to normal operation; must not be left floating. |
| 6 | CD | output | HART mode: carrier detect, logic high indicates a valid carrier is present. FF or PA mode: while not transmitting, high indicates a valid carrier; while transmitting, high indicates the jabber inhibitor has triggered. |
| 7 | UART_IN | input | UART data input; must not be left floating. |
| 8 | UART_RTS | bidirectional | HART mode: logic high enables the demodulator and disables the modulator, logic low does the reverse. FF or PA mode: reports transmit FIFO threshold information as programmed by the packet initiation code. |
| 9 | DUPLEX | input | Logic high enables full-duplex (internal loop-back) test mode; must not be left floating. |
| 10 | UART_OUT | output | UART data output. |
| 11 | IOVDD | power_in | Interface supply for digital input and output circuitry; this voltage sets the logical thresholds for the digital interface. |
| 12 | GND | power_in | Digital ground, the ground reference for all digital circuitry of the device. |
| 13 | REG_CAP | output | Capacitor connection for the internal regulator. |
| 14 | MOD_OUT | output | Modem output: FSK sinusoid in HART mode or Manchester coded data in FOUNDATION Fieldbus and PROFIBUS PA modes; requires 5 nF to 22 nF parallel capacitance in HART mode, or 0 pF to 100 pF in FF/PA mode. |
| 15 | REF | bidirectional | Outputs the internal reference voltage when the internal reference is enabled; is the external 2.5-V reference input when the internal reference is disabled. |
| 16 | MOD_IN | input | HART FSK input or FOUNDATION Fieldbus/PROFIBUS PA Manchester data input; do not connect this pin if an external filter is used. |
| 17 | MOD_INF | input | With the internal band-pass filter, connect 680 pF in HART mode or 120 pF in FF/PA mode; with an external filter, connect that filter's output here. |
| 18 | AVDD | power_in | Power supply for the analog circuitry of the device. |
| 19 | GND | power_in | Analog ground, the ground reference for the power supply input. |
| 20 | X2 | input | Crystal stimulus connection for the crystal oscillator. |
| 21 | X1 | input | Crystal drive or external clock input. |
| 22 | GND | power_in | Digital ground, the ground reference for all digital circuitry of the device. |
| 23 | REF_EN | input | Logic high enables the internal 1.5-V reference; must not be left floating. |
| 24 | BPF_EN | input | Logic high enables the internal band-pass filter; must not be left floating. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFN-24-EP(4x4) |
| Category | Interface ICs |
| Pins | 25 |

## CAD (KiCad official)

- Symbol: `DAC8740HRGET`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: TQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `dac8740hrget-etched.step` / `dac8740hrget-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8740hrget.step` / `dac8740hrget.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac8740hrget.pdf) (49 pp, sha256 `ee898989d48c115d`, retrieved 2026-10-30, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dac8740hrget-datasheet.pdf)