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DAC8740HRGER

Public Made by Adom

by adom

Texas Instruments Interface - Specialized, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DAC8740HRGER

Texas Instruments · Interface - Specialized · VQFN-24-EP(4x4)

DAC8740HRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XEN input Crystal oscillator enable; logic low enables external crystal oscillator circuit, logic high disables it requiring external CMOS clock or internal oscillator. No digital input pin should be left floating.
2 CLKO output Clock output; can be configured as clock output when using internal oscillator or external crystal oscillator.
3 CLK_CFG0 input Clock configuration input; used to configure input/output clocking scheme. No digital input pin should be left floating.
4 CLK_CFG1 input Clock configuration input; used to configure input/output clocking scheme. No digital input pin should be left floating.
5 RST input Reset input; logic low places device into power-down mode and resets the device, logic high returns device to normal operation. No digital input pin should be left floating.
6 CD output Carrier detect output; logic high indicates valid carrier is present in HART mode, or indicates jabber inhibitor has triggered in FF/PA mode.
7 UART_IN input UART data input; serial data input for UART interface. No digital input pin should be left floating.
8 UART_RTS bidirectional UART request to send; in HART mode, logic high enables demodulator and disables modulator, logic low enables modulator and disables demodulator; in FF/PA mode, reports transmit FIFO threshold information. No digital input pin should be left floating.
9 DUPLEX input Full-duplex mode enable input; logic high enables full-duplex or internal loop-back test mode. No digital input pin should be left floating.
10 UART_OUT output UART data output; serial data output from UART interface.
11 IOVDD power_in Interface supply voltage; 1.71V to 5.5V supply for digital input and output circuitry, sets logical thresholds for digital interface.
12 GND power_in Digital ground; ground reference voltage for all digital circuitry of the device.
13 REG_CAP passive Internal regulator capacitor pad; connect capacitor for internal regulator.
14 MOD_OUT output Modem output; FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes; requires parallel capacitance of 5-22nF in HART mode or 0-100pF in FF/PA mode for stability.
15 REF bidirectional Voltage reference; when internal reference enabled, outputs internal 1.5V reference voltage; when internal reference disabled, accepts external 2.5V reference input.
16 MOD_IN input Modem input; HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. Do not connect if external filter is used.
17 MOD_INF input Filtered modem input; when using internal band-pass filter, connect 680pF to pin in HART mode or 120pF in FF/PA modes; when using external filter, connect output of external filter to this pin.
18 AVDD power_in Analog power supply; 2.7V to 5.5V supply voltage for analog circuitry of the device.
19 GND power_in Analog ground; ground reference voltage for power supply input.
20 X2 input Crystal oscillator stimulus input; second terminal of external crystal oscillator.
21 X1 input Crystal or clock input; first terminal of external crystal oscillator or external CMOS clock input.
22 GND power_in Digital ground; ground reference voltage for all digital circuitry of the device.
23 REF_EN input Reference enable input; logic high enables internal 1.5V reference. No digital input pin should be left floating.
24 BPF_EN input Band-pass filter enable input; logic high enables internal band-pass filter. No digital input pin should be left floating.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Communication Interface Chip/UART/485/232
Pins 25

CAD (KiCad official)

  • Symbol: DAC8740HRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: dac8740hrger-etched.step / dac8740hrger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8740hrger.step / dac8740hrger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 4cde27aab0a7c3d9, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF