component
DAC8740HRGER
Public Made by Adomby adom
Texas Instruments Interface - Specialized, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# DAC8740HRGER++**Texas Instruments** · Interface - Specialized · VQFN-24-EP(4x4)++DAC8740HRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | XEN | input | Crystal oscillator enable; logic low enables external crystal oscillator circuit, logic high disables it requiring external CMOS clock or internal oscillator. No digital input pin should be left floating. |+| 2 | CLKO | output | Clock output; can be configured as clock output when using internal oscillator or external crystal oscillator. |+| 3 | CLK_CFG0 | input | Clock configuration input; used to configure input/output clocking scheme. No digital input pin should be left floating. |+| 4 | CLK_CFG1 | input | Clock configuration input; used to configure input/output clocking scheme. No digital input pin should be left floating. |+| 5 | RST | input | Reset input; logic low places device into power-down mode and resets the device, logic high returns device to normal operation. No digital input pin should be left floating. |+| 6 | CD | output | Carrier detect output; logic high indicates valid carrier is present in HART mode, or indicates jabber inhibitor has triggered in FF/PA mode. |+| 7 | UART_IN | input | UART data input; serial data input for UART interface. No digital input pin should be left floating. |+| 8 | UART_RTS | bidirectional | UART request to send; in HART mode, logic high enables demodulator and disables modulator, logic low enables modulator and disables demodulator; in FF/PA mode, reports transmit FIFO threshold information. No digital input pin should be left floating. |+| 9 | DUPLEX | input | Full-duplex mode enable input; logic high enables full-duplex or internal loop-back test mode. No digital input pin should be left floating. |+| 10 | UART_OUT | output | UART data output; serial data output from UART interface. |+| 11 | IOVDD | power_in | Interface supply voltage; 1.71V to 5.5V supply for digital input and output circuitry, sets logical thresholds for digital interface. |+| 12 | GND | power_in | Digital ground; ground reference voltage for all digital circuitry of the device. |+| 13 | REG_CAP | passive | Internal regulator capacitor pad; connect capacitor for internal regulator. |+| 14 | MOD_OUT | output | Modem output; FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes; requires parallel capacitance of 5-22nF in HART mode or 0-100pF in FF/PA mode for stability. |+| 15 | REF | bidirectional | Voltage reference; when internal reference enabled, outputs internal 1.5V reference voltage; when internal reference disabled, accepts external 2.5V reference input. |+| 16 | MOD_IN | input | Modem input; HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. Do not connect if external filter is used. |+| 17 | MOD_INF | input | Filtered modem input; when using internal band-pass filter, connect 680pF to pin in HART mode or 120pF in FF/PA modes; when using external filter, connect output of external filter to this pin. |+| 18 | AVDD | power_in | Analog power supply; 2.7V to 5.5V supply voltage for analog circuitry of the device. |+| 19 | GND | power_in | Analog ground; ground reference voltage for power supply input. |+| 20 | X2 | input | Crystal oscillator stimulus input; second terminal of external crystal oscillator. |+| 21 | X1 | input | Crystal or clock input; first terminal of external crystal oscillator or external CMOS clock input. |+| 22 | GND | power_in | Digital ground; ground reference voltage for all digital circuitry of the device. |+| 23 | REF_EN | input | Reference enable input; logic high enables internal 1.5V reference. No digital input pin should be left floating. |+| 24 | BPF_EN | input | Band-pass filter enable input; logic high enables internal band-pass filter. No digital input pin should be left floating. |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24-EP(4x4) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `DAC8740HRGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`+- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `dac8740hrger-etched.step` / `dac8740hrger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8740hrger.step` / `dac8740hrger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8740h) (48 pp, sha256 `4cde27aab0a7c3d9`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac8740hrger-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "dac8740hrger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac8740hrger.kicad_sym",+ "dac8740hrger.kicad_mod",+ "dac8740hrger.glb",+ "dac8740hrger.step",+ "dac8740hrger.lbr",+ "docs/hero.png",+ "docs/dac8740hrger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac8740hrger-hero.glb",+ "dac8740hrger-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC8740HRGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 25,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "Interface - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac8740h",+ "parts": {+ "symbol": "dac8740hrger.kicad_sym",+ "footprint": "dac8740hrger.kicad_mod",+ "model_3d": "dac8740hrger-hero.glb",+ "model_3d_plain": "dac8740hrger.glb",+ "model_3d_step": "dac8740hrger-etched.step",+ "model_3d_step_plain": "dac8740hrger.step",+ "lbr": "dac8740hrger.lbr"+ },+ "distributor_links": {+ "lcsc": "C2674248",+ "digikey": "DAC8740HRGER-ND",+ "mouser": "595-DAC8740HRGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T01:25:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "DAC8740HRGER-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DAC8740HRGER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "XEN",+ "type": "input",+ "description": "Crystal oscillator enable; logic low enables external crystal oscillator circuit, logic high disables it requiring external CMOS clock or internal oscillator. No digital input pin should be left floating."+ },+ {+ "number": "2",+ "name": "CLKO",+ "type": "output",+ "description": "Clock output; can be configured as clock output when using internal oscillator or external crystal oscillator."+ },+ {+ "number": "3",+ "name": "CLK_CFG0",+ "type": "input",+ "description": "Clock configuration input; used to configure input/output clocking scheme. No digital input pin should be left floating."+ },+ {+ "number": "4",+ "name": "CLK_CFG1",+ "type": "input",+ "description": "Clock configuration input; used to configure input/output clocking scheme. No digital input pin should be left floating."+ },+ {+ "number": "5",+ "name": "RST",+ "type": "input",+ "description": "Reset input; logic low places device into power-down mode and resets the device, logic high returns device to normal operation. No digital input pin should be left floating."+ },+ {+ "number": "6",+ "name": "CD",+ "type": "output",+ "description": "Carrier detect output; logic high indicates valid carrier is present in HART mode, or indicates jabber inhibitor has triggered in FF/PA mode."+ },+ {+ "number": "7",+ "name": "UART_IN",+ "type": "input",+ "description": "UART data input; serial data input for UART interface. No digital input pin should be left floating."+ },+ {+ "number": "8",+ "name": "UART_RTS",+ "type": "bidirectional",+ "description": "UART request to send; in HART mode, logic high enables demodulator and disables modulator, logic low enables modulator and disables demodulator; in FF/PA mode, reports transmit FIFO threshold information. No digital input pin should be left floating."+ },+ {+ "number": "9",+ "name": "DUPLEX",+ "type": "input",+ "description": "Full-duplex mode enable input; logic high enables full-duplex or internal loop-back test mode. No digital input pin should be left floating."+ },+ {+ "number": "10",+ "name": "UART_OUT",+ "type": "output",+ "description": "UART data output; serial data output from UART interface."+ },+ {+ "number": "11",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Interface supply voltage; 1.71V to 5.5V supply for digital input and output circuitry, sets logical thresholds for digital interface."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground; ground reference voltage for all digital circuitry of the device."+ },+ {+ "number": "13",+ "name": "REG_CAP",+ "type": "passive",+ "description": "Internal regulator capacitor pad; connect capacitor for internal regulator."+ },+ {+ "number": "14",+ "name": "MOD_OUT",+ "type": "output",+ "description": "Modem output; FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes; requires parallel capacitance of 5-22nF in HART mode or 0-100pF in FF/PA mode for stability."+ },+ {+ "number": "15",+ "name": "REF",+ "type": "bidirectional",+ "description": "Voltage reference; when internal reference enabled, outputs internal 1.5V reference voltage; when internal reference disabled, accepts external 2.5V reference input."+ },+ {+ "number": "16",+ "name": "MOD_IN",+ "type": "input",+ "description": "Modem input; HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. Do not connect if external filter is used."+ },+ {+ "number": "17",+ "name": "MOD_INF",+ "type": "input",+ "description": "Filtered modem input; when using internal band-pass filter, connect 680pF to pin in HART mode or 120pF in FF/PA modes; when using external filter, connect output of external filter to this pin."+ },+ {+ "number": "18",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply; 2.7V to 5.5V supply voltage for analog circuitry of the device."+ },+ {+ "number": "19",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground; ground reference voltage for power supply input."+ },+ {+ "number": "20",+ "name": "X2",+ "type": "input",+ "description": "Crystal oscillator stimulus input; second terminal of external crystal oscillator."+ },+ {+ "number": "21",+ "name": "X1",+ "type": "input",+ "description": "Crystal or clock input; first terminal of external crystal oscillator or external CMOS clock input."+ },+ {+ "number": "22",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground; ground reference voltage for all digital circuitry of the device."+ },+ {+ "number": "23",+ "name": "REF_EN",+ "type": "input",+ "description": "Reference enable input; logic high enables internal 1.5V reference. No digital input pin should be left floating."+ },+ {+ "number": "24",+ "name": "BPF_EN",+ "type": "input",+ "description": "Band-pass filter enable input; logic high enables internal band-pass filter. No digital input pin should be left floating."+ },+ {+ "number": "25",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 17,+ "cost_usd": 0.1605,+ "at": "2026-10-07T01:24:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac8740h",+ "pages": 48,+ "sha256": "4cde27aab0a7c3d9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac8740hrger.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac8740hrger-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "001a78ce452cd79a1c68a932186de85d6bff10eff75e943db6f9022c6ece916b",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}