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DAC8568IDPWR
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Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DAC8568IDPWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC8568IDPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Load DACs input; it is a negative-edge triggered signal for simultaneous DAC updates in asynchronous mode, and must be connected to GND permanently when using synchronous update mode. |
| 2 | SYNC | input | Active-low, level-triggered Schmitt-trigger frame synchronization input that enables the input shift register, with the DAC output updating after the 32nd SCLK falling edge and a SYNC rising edge before the 31st clock edge aborting the write. |
| 3 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |
| 4 | VOUTA | output | Analog output voltage from DAC A. |
| 5 | VOUTC | output | Analog output voltage from DAC C. |
| 6 | VOUTE | output | Analog output voltage from DAC E. |
| 7 | VOUTG | output | Analog output voltage from DAC G. |
| 8 | VREFIN/VREFOUT | bidirectional | Positive reference input or reference output, which is 2.5 V when the internal reference is used; external VREFIN maximum is AVDD for grades A and B and AVDD/2 for grades C and D. |
| 9 | CLR | input | Asynchronous, falling-edge triggered clear input that clears all DAC registers and buffers to the clear code, with a minimum low pulse width of 80 ns. |
| 10 | VOUTH | output | Analog output voltage from DAC H. |
| 11 | VOUTF | output | Analog output voltage from DAC F. |
| 12 | VOUTD | output | Analog output voltage from DAC D. |
| 13 | VOUTB | output | Analog output voltage from DAC B. |
| 14 | GND | power_in | Ground reference point for all circuitry on the device. |
| 15 | DIN | input | Serial data input clocked into the 32-bit input shift register on each SCLK falling edge; Schmitt-trigger logic input. |
| 16 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz; Schmitt-trigger logic input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy (INL) | -12 | 4 | 12 | LSB | Measured by the line passing through codes 485 and 64714 | 5 | |
| Differential nonlinearity | -1 | 0.2 | 1 | LSB | 16-bit monotonic | 5 | |
| Offset error | -4 | 1 | 4 | mV | Extrapolated from two-point line, unloaded | 5 | |
| Offset error drift | -0.5 | 0.5 | μV/°C | 5 | |||
| Zero-code error | 1 | 4 | mV | DAC register loaded with all '0's | 5 | ||
| Zero-code error drift | -2 | 2 | μV/°C | 5 | |||
| Full-scale error | -0.2 | 0.03 | 0.2 | % of FSR | DAC register loaded with all '1's | 5 | |
| Gain error | -0.15 | 0.01 | 0.15 | % of FSR | Extrapolated from two-point line, unloaded | 5 | |
| Gain temperature coefficient | -1 | 1 | ppm of FSR/°C | 5 | |||
| Output voltage range | 0 | V | AVDD ≥ 5V; grades C and D; maximum output voltage 5V when using internal reference (printed max = AVDD) | 6 | |||
| Output voltage settling time | 5 | 10 | μs | DACs unloaded; 1/4 scale to 3/4 scale to ±0.024% | 6 | ||
| Capacitive load stability | 1000 | pF | RL = ∞ | 6 | |||
| Capacitive load stability | 3000 | pF | RL = 2kΩ | 6 | |||
| Output current load capability | -20 | 20 | mA | 7 | |||
| VREFIN reference input range | VREFIN | 0 | V | Grades C/D, AVDD = 5.0V to 5.5V (printed max = AVDD/2) | 6 | ||
| Reference output voltage | 2.4975 | 2.5 | 2.5025 | V | TA = +25°C; all grades | 6 | |
| Reference initial accuracy | -0.1 | 0.004 | 0.1 | % | TA = +25°C, all grades | 6 | |
| Reference output voltage temperature drift | 2 | 5 | ppm/°C | Grades C/D | 6 | ||
| Logic input current | -1 | 1 | μA | 7 | |||
| Supply voltage AVDD | AVDD | 2.7 | 5.5 | V | 7 | ||
| Supply current, normal mode, internal reference off | IDD | 0.95 | 1.4 | mA | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 | |
| Supply current, normal mode, internal reference off | IDD | 0.81 | 1.3 | mA | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 | |
| Supply current, normal mode, internal reference on | IDD | 1.25 | 2.5 | mA | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 | |
| Supply current, normal mode, internal reference on | IDD | 1.1 | 1.9 | mA | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 | |
| Supply current, all power-down modes | IDD | 0.18 | 3 | μA | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 | |
| Supply current, all power-down modes | IDD | 0.1 | 2.5 | μA | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 | |
| Power dissipation, normal mode, internal reference off | 3.4 | 7.7 | mW | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 | ||
| Power dissipation, normal mode, internal reference off | 2.2 | 4.7 | mW | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 | ||
| Power dissipation, normal mode, internal reference on | 4.5 | 11 | mW | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 | ||
| Power dissipation, normal mode, internal reference on | 2.9 | 6.8 | mW | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 | ||
| Power dissipation, all power-down modes | 0.6 | 16 | μW | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 | ||
| Power dissipation, all power-down modes | 0.3 | 9 | μW | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 | ||
| Specified performance temperature range | -40 | 125 | °C | 7 | |||
| AVDD to GND | AVDD | -0.3 | 6 | V | 5 | ||
| Digital input voltage to GND | -0.3 | V | Printed max = AVDD + 0.3 | 5 | |||
| VOUT to GND | VOUT | -0.3 | V | Printed max = AVDD + 0.3 | 5 | ||
| VREF to GND | VREF | -0.3 | V | Printed max = AVDD + 0.3 | 5 | ||
| Operating temperature range | -40 | 125 | °C | 5 | |||
| Storage temperature range | -65 | 150 | °C | 5 | |||
| Junction temperature range (TJ max) | TJ | 150 | °C | 5 | |||
| Thermal impedance, junction-to-ambient | RθJA | 118 | °C/W | 5 | |||
| Thermal impedance, junction-to-case | RθJC | 29 | °C/W | 5 | |||
| SCLK falling edge to SYNC falling edge | t1 | 10 | ns | AVDD = 2.7V to 5.5V | 7 | ||
| SCLK cycle time | t2 | 20 | ns | AVDD = 2.7V to 5.5V | 7 | ||
| SYNC rising edge to 31st SCLK falling edge | t3 | 13 | ns | AVDD = 2.7V to 5.5V | 7 | ||
| Minimum SYNC HIGH time | t4 | 80 | ns | AVDD = 2.7V to 5.5V | 7 | ||
| SYNC to SCLK falling edge setup time | t5 | 13 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| SCLK LOW time | t6 | 8 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| SCLK HIGH time | t7 | 8 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| SCLK falling edge to SYNC rising edge | t8 | 10 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| Data setup time | t9 | 6 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| Data hold time | t10 | 4 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| SCLK falling edge to LDAC falling edge (asynchronous LDAC) | t11 | 40 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| LDAC pulse width LOW time | t12 | 80 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| 32nd SCLK falling edge to LDAC rising edge | t14 | 40 | ns | AVDD = 2.7V to 5.5V | 8 | ||
| CLR pulse width LOW time | t15 | 80 | ns | AVDD = 2.7V to 5.5V | 8 |
CAD (KiCad official)
- Symbol:
DAC8568IDPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac8568idpwr-etched.step/dac8568idpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8568idpwr.step/dac8568idpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (72 pp, sha256
d1ab4f63d58b4e3b, retrieved 2026-11-10, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC8568IDPWR
**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16
DAC8568IDPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Load DACs input; it is a negative-edge triggered signal for simultaneous DAC updates in asynchronous mode, and must be connected to GND permanently when using synchronous update mode. |
| 2 | SYNC | input | Active-low, level-triggered Schmitt-trigger frame synchronization input that enables the input shift register, with the DAC output updating after the 32nd SCLK falling edge and a SYNC rising edge before the 31st clock edge aborting the write. |
| 3 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |
| 4 | VOUTA | output | Analog output voltage from DAC A. |
| 5 | VOUTC | output | Analog output voltage from DAC C. |
| 6 | VOUTE | output | Analog output voltage from DAC E. |
| 7 | VOUTG | output | Analog output voltage from DAC G. |
| 8 | VREFIN/VREFOUT | bidirectional | Positive reference input or reference output, which is 2.5 V when the internal reference is used; external VREFIN maximum is AVDD for grades A and B and AVDD/2 for grades C and D. |
| 9 | CLR | input | Asynchronous, falling-edge triggered clear input that clears all DAC registers and buffers to the clear code, with a minimum low pulse width of 80 ns. |
| 10 | VOUTH | output | Analog output voltage from DAC H. |
| 11 | VOUTF | output | Analog output voltage from DAC F. |
| 12 | VOUTD | output | Analog output voltage from DAC D. |
| 13 | VOUTB | output | Analog output voltage from DAC B. |
| 14 | GND | power_in | Ground reference point for all circuitry on the device. |
| 15 | DIN | input | Serial data input clocked into the 32-bit input shift register on each SCLK falling edge; Schmitt-trigger logic input. |
| 16 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz; Schmitt-trigger logic input. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy (INL) | | -12 | 4 | 12 | LSB | Measured by the line passing through codes 485 and 64714 | 5 |
| Differential nonlinearity | | -1 | 0.2 | 1 | LSB | 16-bit monotonic | 5 |
| Offset error | | -4 | 1 | 4 | mV | Extrapolated from two-point line, unloaded | 5 |
| Offset error drift | | -0.5 | | 0.5 | μV/°C | | 5 |
| Zero-code error | | | 1 | 4 | mV | DAC register loaded with all '0's | 5 |
| Zero-code error drift | | -2 | | 2 | μV/°C | | 5 |
| Full-scale error | | -0.2 | 0.03 | 0.2 | % of FSR | DAC register loaded with all '1's | 5 |
| Gain error | | -0.15 | 0.01 | 0.15 | % of FSR | Extrapolated from two-point line, unloaded | 5 |
| Gain temperature coefficient | | -1 | | 1 | ppm of FSR/°C | | 5 |
| Output voltage range | | 0 | | | V | AVDD ≥ 5V; grades C and D; maximum output voltage 5V when using internal reference (printed max = AVDD) | 6 |
| Output voltage settling time | | | 5 | 10 | μs | DACs unloaded; 1/4 scale to 3/4 scale to ±0.024% | 6 |
| Capacitive load stability | | | | 1000 | pF | RL = ∞ | 6 |
| Capacitive load stability | | | | 3000 | pF | RL = 2kΩ | 6 |
| Output current load capability | | -20 | | 20 | mA | | 7 |
| VREFIN reference input range | VREFIN | 0 | | | V | Grades C/D, AVDD = 5.0V to 5.5V (printed max = AVDD/2) | 6 |
| Reference output voltage | | 2.4975 | 2.5 | 2.5025 | V | TA = +25°C; all grades | 6 |
| Reference initial accuracy | | -0.1 | 0.004 | 0.1 | % | TA = +25°C, all grades | 6 |
| Reference output voltage temperature drift | | | 2 | 5 | ppm/°C | Grades C/D | 6 |
| Logic input current | | -1 | | 1 | μA | | 7 |
| Supply voltage AVDD | AVDD | 2.7 | | 5.5 | V | | 7 |
| Supply current, normal mode, internal reference off | IDD | | 0.95 | 1.4 | mA | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 |
| Supply current, normal mode, internal reference off | IDD | | 0.81 | 1.3 | mA | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 |
| Supply current, normal mode, internal reference on | IDD | | 1.25 | 2.5 | mA | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 |
| Supply current, normal mode, internal reference on | IDD | | 1.1 | 1.9 | mA | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 |
| Supply current, all power-down modes | IDD | | 0.18 | 3 | μA | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 |
| Supply current, all power-down modes | IDD | | 0.1 | 2.5 | μA | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 |
| Power dissipation, normal mode, internal reference off | | | 3.4 | 7.7 | mW | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 |
| Power dissipation, normal mode, internal reference off | | | 2.2 | 4.7 | mW | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 |
| Power dissipation, normal mode, internal reference on | | | 4.5 | 11 | mW | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 |
| Power dissipation, normal mode, internal reference on | | | 2.9 | 6.8 | mW | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 |
| Power dissipation, all power-down modes | | | 0.6 | 16 | μW | AVDD = 3.6V to 5.5V; VINH = AVDD and VINL = GND | 7 |
| Power dissipation, all power-down modes | | | 0.3 | 9 | μW | AVDD = 2.7V to 3.6V; VINH = AVDD and VINL = GND | 7 |
| Specified performance temperature range | | -40 | | 125 | °C | | 7 |
| AVDD to GND | AVDD | -0.3 | | 6 | V | | 5 |
| Digital input voltage to GND | | -0.3 | | | V | Printed max = AVDD + 0.3 | 5 |
| VOUT to GND | VOUT | -0.3 | | | V | Printed max = AVDD + 0.3 | 5 |
| VREF to GND | VREF | -0.3 | | | V | Printed max = AVDD + 0.3 | 5 |
| Operating temperature range | | -40 | | 125 | °C | | 5 |
| Storage temperature range | | -65 | | 150 | °C | | 5 |
| Junction temperature range (TJ max) | TJ | | | 150 | °C | | 5 |
| Thermal impedance, junction-to-ambient | RθJA | | 118 | | °C/W | | 5 |
| Thermal impedance, junction-to-case | RθJC | | 29 | | °C/W | | 5 |
| SCLK falling edge to SYNC falling edge | t1 | 10 | | | ns | AVDD = 2.7V to 5.5V | 7 |
| SCLK cycle time | t2 | 20 | | | ns | AVDD = 2.7V to 5.5V | 7 |
| SYNC rising edge to 31st SCLK falling edge | t3 | 13 | | | ns | AVDD = 2.7V to 5.5V | 7 |
| Minimum SYNC HIGH time | t4 | 80 | | | ns | AVDD = 2.7V to 5.5V | 7 |
| SYNC to SCLK falling edge setup time | t5 | 13 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| SCLK LOW time | t6 | 8 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| SCLK HIGH time | t7 | 8 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| SCLK falling edge to SYNC rising edge | t8 | 10 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| Data setup time | t9 | 6 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| Data hold time | t10 | 4 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| SCLK falling edge to LDAC falling edge (asynchronous LDAC) | t11 | 40 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| LDAC pulse width LOW time | t12 | 80 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| 32nd SCLK falling edge to LDAC rising edge | t14 | 40 | | | ns | AVDD = 2.7V to 5.5V | 8 |
| CLR pulse width LOW time | t15 | 80 | | | ns | AVDD = 2.7V to 5.5V | 8 |
## CAD (KiCad official)
- Symbol: `DAC8568IDPWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `dac8568idpwr-etched.step` / `dac8568idpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8568idpwr.step` / `dac8568idpwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac8568.pdf) (72 pp, sha256 `d1ab4f63d58b4e3b`, retrieved 2026-11-10, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac8568idpwr-datasheet.pdf)