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DAC8568IAPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# DAC8568IAPWR++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16++DAC8568IAPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LDAC | input | Load DACs; negative edge-triggered control input that simultaneously updates selected DAC output registers from their input buffers. |+| 2 | SYNC | input | Frame synchronization signal (active low) that enables the input shift register; DAC output updates following the 32nd clock edge; Schmitt-Trigger input. |+| 3 | AVDD | power_in | Power supply input; operating voltage range 2.7V to 5.5V. |+| 4 | VOUTA | output | Analog output voltage from DAC A; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 5 | VOUTC | output | Analog output voltage from DAC C; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 6 | VOUTE | output | Analog output voltage from DAC E; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 7 | VOUTG | output | Analog output voltage from DAC G; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 8 | VREFIN/VREFOUT | bidirectional | Positive reference input or 2.5V internal reference output; external reference range 0 to AVDD for grades A/B with 20mA source/sink capability. |+| 9 | CLR | input | Asynchronous clear input (active low) that resets all DAC registers and buffers to the value specified in the clear code register. |+| 10 | VOUTH | output | Analog output voltage from DAC H; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 11 | VOUTF | output | Analog output voltage from DAC F; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 12 | VOUTD | output | Analog output voltage from DAC D; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 13 | VOUTB | output | Analog output voltage from DAC B; output range 0V to AVDD with typical slew rate 0.75V/μs. |+| 14 | GND | power_in | Ground reference point; 0V reference for all analog and digital circuitry on the device. |+| 15 | DIN | input | Serial data input; data are clocked into the 32-bit input shift register on each falling edge of SCLK with Schmitt-Trigger input. |+| 16 | SCLK | input | Serial clock input; data transfer rates up to 50MHz with Schmitt-Trigger input; typical clock period 20ns minimum. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `DAC8568IAPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `dac8568iapwr-etched.step` / `dac8568iapwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8568iapwr.step` / `dac8568iapwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8568) (72 pp, sha256 `e14f8beb0a8c704b`, retrieved 2026-09-26, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac8568iapwr-datasheet.pdf)
page.jsonadded+204@@ -0,0 +1,204 @@+{+ "slug": "dac8568iapwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac8568iapwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac8568iapwr.kicad_sym",+ "dac8568iapwr.kicad_mod",+ "dac8568iapwr.glb",+ "dac8568iapwr.step",+ "dac8568iapwr.lbr",+ "docs/hero.png",+ "docs/dac8568iapwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DAC8568IAPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac8568",+ "parts": {+ "symbol": "dac8568iapwr.kicad_sym",+ "footprint": "dac8568iapwr.kicad_mod",+ "model_3d": "dac8568iapwr-etched.glb",+ "model_3d_plain": "dac8568iapwr.glb",+ "model_3d_step": "dac8568iapwr-etched.step",+ "model_3d_step_plain": "dac8568iapwr.step",+ "lbr": "dac8568iapwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C486051",+ "digikey": "DAC8568IAPWR-ND",+ "mouser": "595-DAC8568IAPWR"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T12:12:23Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "DAC8568IAPWR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DAC8568IAPWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LDAC",+ "type": "input",+ "description": "Load DACs; negative edge-triggered control input that simultaneously updates selected DAC output registers from their input buffers."+ },+ {+ "number": "2",+ "name": "SYNC",+ "type": "input",+ "description": "Frame synchronization signal (active low) that enables the input shift register; DAC output updates following the 32nd clock edge; Schmitt-Trigger input."+ },+ {+ "number": "3",+ "name": "AVDD",+ "type": "power_in",+ "description": "Power supply input; operating voltage range 2.7V to 5.5V."+ },+ {+ "number": "4",+ "name": "VOUTA",+ "type": "output",+ "description": "Analog output voltage from DAC A; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "5",+ "name": "VOUTC",+ "type": "output",+ "description": "Analog output voltage from DAC C; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "6",+ "name": "VOUTE",+ "type": "output",+ "description": "Analog output voltage from DAC E; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "7",+ "name": "VOUTG",+ "type": "output",+ "description": "Analog output voltage from DAC G; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "8",+ "name": "VREFIN/VREFOUT",+ "type": "bidirectional",+ "description": "Positive reference input or 2.5V internal reference output; external reference range 0 to AVDD for grades A/B with 20mA source/sink capability."+ },+ {+ "number": "9",+ "name": "CLR",+ "type": "input",+ "description": "Asynchronous clear input (active low) that resets all DAC registers and buffers to the value specified in the clear code register."+ },+ {+ "number": "10",+ "name": "VOUTH",+ "type": "output",+ "description": "Analog output voltage from DAC H; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "11",+ "name": "VOUTF",+ "type": "output",+ "description": "Analog output voltage from DAC F; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "12",+ "name": "VOUTD",+ "type": "output",+ "description": "Analog output voltage from DAC D; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "13",+ "name": "VOUTB",+ "type": "output",+ "description": "Analog output voltage from DAC B; output range 0V to AVDD with typical slew rate 0.75V/μs."+ },+ {+ "number": "14",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point; 0V reference for all analog and digital circuitry on the device."+ },+ {+ "number": "15",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input; data are clocked into the 32-bit input shift register on each falling edge of SCLK with Schmitt-Trigger input."+ },+ {+ "number": "16",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input; data transfer rates up to 50MHz with Schmitt-Trigger input; typical clock period 20ns minimum."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 72,+ "cost_usd": 0.5922,+ "at": "2026-09-26T12:12:03"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac8568",+ "pages": 72,+ "sha256": "e14f8beb0a8c704b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}