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DAC8568IAPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC8568IAPWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC8568IAPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Load DACs; negative edge-triggered control input that simultaneously updates selected DAC output registers from their input buffers. |
| 2 | SYNC | input | Frame synchronization signal (active low) that enables the input shift register; DAC output updates following the 32nd clock edge; Schmitt-Trigger input. |
| 3 | AVDD | power_in | Power supply input; operating voltage range 2.7V to 5.5V. |
| 4 | VOUTA | output | Analog output voltage from DAC A; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 5 | VOUTC | output | Analog output voltage from DAC C; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 6 | VOUTE | output | Analog output voltage from DAC E; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 7 | VOUTG | output | Analog output voltage from DAC G; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 8 | VREFIN/VREFOUT | bidirectional | Positive reference input or 2.5V internal reference output; external reference range 0 to AVDD for grades A/B with 20mA source/sink capability. |
| 9 | CLR | input | Asynchronous clear input (active low) that resets all DAC registers and buffers to the value specified in the clear code register. |
| 10 | VOUTH | output | Analog output voltage from DAC H; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 11 | VOUTF | output | Analog output voltage from DAC F; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 12 | VOUTD | output | Analog output voltage from DAC D; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 13 | VOUTB | output | Analog output voltage from DAC B; output range 0V to AVDD with typical slew rate 0.75V/μs. |
| 14 | GND | power_in | Ground reference point; 0V reference for all analog and digital circuitry on the device. |
| 15 | DIN | input | Serial data input; data are clocked into the 32-bit input shift register on each falling edge of SCLK with Schmitt-Trigger input. |
| 16 | SCLK | input | Serial clock input; data transfer rates up to 50MHz with Schmitt-Trigger input; typical clock period 20ns minimum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC8568IAPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac8568iapwr-etched.step/dac8568iapwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8568iapwr.step/dac8568iapwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (72 pp, sha256
e14f8beb0a8c704b, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).