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DAC8565IDPWR

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Texas Instruments Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiondac8565idpwrfactory-2.0.0extractor-text

Verified DAC8565IDPWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC8565IDPWR · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 51-page datasheet
  • ✓distributor: lcsc C2864688, digikey 296-DAC8565IDPWRTR-ND, mouser 595-DAC8565IDPWR
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rooml0s3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.48)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac8565idpwr.kicad_sym✓ dac8565idpwr.kicad_mod✓ dac8565idpwr.step
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Ray Publish 0.1.0 a08e8e2 7d ago

DAC8565IDPWR

Texas Instruments · Digital To Analog Converters (DACs) · TSSOP-16

DAC8565IDPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A.
2 VOUTB output Analog output voltage from DAC B.
3 VREFH/VREFOUT bidirectional Positive reference input, or 2.5V reference output when the internal reference is used.
4 AVDD power_in Power-supply input, 2.7V to 5.5V.
5 VREFL input Negative reference input.
6 GND power_in Ground reference point for all circuitry on the part.
7 VOUTC output Analog output voltage from DAC C.
8 VOUTD output Analog output voltage from DAC D.
9 SYNC input Active-low level-triggered frame synchronization input with Schmitt-trigger logic; going low enables the input shift register, the DAC output updates following the 24th clock, and taking SYNC high before the 24th clock edge interrupts and ignores the write sequence.
10 SCLK input Serial clock input with Schmitt-trigger logic, data transfer at rates up to 50MHz.
11 DIN input Serial data input with Schmitt-trigger logic, clocked into the 24-bit input shift register on each falling edge of the serial clock.
12 IOVDD power_in Digital input-output power supply, 1.8V to 5.5V.
13 RST input Asynchronous active-low reset; when low, all DAC channels reset to zero-scale (RSTSEL = 0) or midscale (RSTSEL = 1).
14 RSTSEL input Reset select; if low, input coding is binary, and if high, two's complement.
15 ENABLE input Active-low enable pin that connects the SPI interface to the serial port.
16 LDAC input Load DACs; rising edge triggered, loads all DAC registers.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to GND AVDD -0.3 6 V 2
Digital input voltage to GND -0.3 V -0.3 to +VDD + 0.3 V 2
VOUT to GND VOUT -0.3 V -0.3 to +VDD + 0.3 V 2
VREF to GND VREF -0.3 V -0.3 to +VDD + 0.3 V 2
Operating temperature range -40 125 °C 2
Storage temperature range -65 150 °C 2
Junction temperature TJ max 150 °C 2
Thermal impedance, junction-to-ambient θJA 118 °C/W 2
Thermal impedance, junction-to-case θJC 29 °C/W 2
ESD HBM 4000 V Human body model 2
ESD CDM 1500 V Charged device model 2
Relative accuracy -8 4 8 LSB DAC8565D; line through codes 485 and 64714 3
Differential nonlinearity DNL -1 0.5 1 LSB 16-bit monotonic 3
Offset error -8 5 8 mV 3
Full-scale error -0.5 0.2 0.5 % of FSR 3
Gain error -0.2 0.05 0.2 % of FSR 3
Output voltage range 0 V 0 to VREF 3
Output voltage settling time 8 10 µs To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ, 0pF < CL < 200pF 3
Reference output voltage 2.4975 2.5 2.5025 V TA = +25°C 4
Reference initial accuracy -0.1 0.004 0.1 % TA = +25°C 4
Reference output voltage temperature drift 2 5 ppm/°C DAC8565C, DAC8565D 4
Logic input current -1 1 µA 4
Logic input LOW voltage VINL 0.3 x IOVDD 2.7V ≤ IOVDD ≤ 5.5V 4
Logic input LOW voltage VINL 0.1 x IOVDD 1.8V ≤ IOVDD ≤ 2.7V 4
Logic input HIGH voltage VINH 0.7 x IOVDD 2.7V ≤ IOVDD ≤ 5.5V 4
Logic input HIGH voltage VINH 0.95 x IOVDD 1.8V ≤ IOVDD ≤ 2.7V 4
Analog supply voltage AVDD 2.7 5.5 V 4
Digital I/O supply voltage IOVDD 1.8 5.5 V 4
IOVDD supply current IOIDD 10 20 µA 4
Supply current, normal mode IDD 1 1.6 mA AVDD = IOVDD = 3.6V to 5.5V; VINH = IOVDD and VINL = GND 4
Supply current, normal mode IDD 0.95 1.5 mA AVDD = IOVDD = 2.7V to 3.6V; VINH = IOVDD and VINL = GND 4
Supply current, all power-down modes IDD 1.3 3.5 µA AVDD = IOVDD = 3.6V to 5.5V; VINH = IOVDD and VINL = GND 4
Supply current, all power-down modes IDD 0.5 2.5 µA AVDD = IOVDD = 2.7V to 3.6V; VINH = IOVDD and VINL = GND 4
Power dissipation, normal mode 3.6 8.8 mW AVDD = IOVDD = 3.6V to 5.5V 4
Power dissipation, normal mode 2.6 5.4 mW AVDD = IOVDD = 2.7V to 3.6V 4
Power dissipation, all power-down modes 4.7 19 µW AVDD = IOVDD = 3.6V to 5.5V 4
Power dissipation, all power-down modes 1.4 9 µW AVDD = IOVDD = 2.7V to 3.6V 4
Specified performance temperature -40 105 °C 4
SCLK cycle time t1 40 ns IOVDD = AVDD = 2.7V to 3.6V 7
SCLK cycle time t1 20 ns IOVDD = AVDD = 3.6V to 5.5V 7
SCLK HIGH time t2 20 ns IOVDD = AVDD = 2.7V to 3.6V 7
SCLK HIGH time t2 10 ns IOVDD = AVDD = 3.6V to 5.5V 7
SCLK LOW time t3 20 ns IOVDD = AVDD = 2.7V to 3.6V 7
SCLK LOW time t3 10 ns IOVDD = AVDD = 3.6V to 5.5V 7
Data setup time t5 5 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
Data hold time t6 4.5 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
Minimum SYNC HIGH time t8 40 ns IOVDD = AVDD = 2.7V to 3.6V 7
Minimum SYNC HIGH time t8 20 ns IOVDD = AVDD = 3.6V to 5.5V 7
24th SCLK falling edge to SYNC falling edge t9 130 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
SYNC rising edge to 24th SCLK falling edge t10 15 ns for successful SYNC interrupt; IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
ENABLE falling edge to SYNC falling edge t11 15 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
24th SCLK falling edge to ENABLE rising edge t12 10 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
24th SCLK falling edge to LDAC rising edge t13 50 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
LDAC rising edge to ENABLE rising edge t14 10 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
LDAC HIGH time t15 10 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
RST rising edge to SYNC falling edge t16 35 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7
RST HIGH time t17 10 ns IOVDD = AVDD = 2.7V to 3.6V and 3.6V to 5.5V 7

CAD (KiCad official)

  • Symbol: DAC8565IDPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: dac8565idpwr-etched.step / dac8565idpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8565idpwr.step / dac8565idpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (51 pp, sha256 41885742ee83df2e, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF