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DAC8565ICPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC8565ICPWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC8565ICPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output from DAC A, output range 0V to VREF with ±20mA drive capability. |
| 2 | VOUTB | output | Analog output from DAC B, output range 0V to VREF with ±20mA drive capability. |
| 3 | VREFH/VREFOUT | bidirectional | Voltage reference input/output; provides 2.5V when internal reference is used, accepts external reference input from 0V to AVDD. |
| 4 | AVDD | power_in | Analog power supply input, operating range 2.7V to 5.5V. |
| 5 | VREFL | input | Negative voltage reference input, accepts 0V to AVDD/2V. |
| 6 | GND | power_in | Ground return for all analog and digital circuitry. |
| 7 | VOUTC | output | Analog output from DAC C, output range 0V to VREF with ±20mA drive capability. |
| 8 | VOUTD | output | Analog output from DAC D, output range 0V to VREF with ±20mA drive capability. |
| 9 | SYNC | input | Level-triggered active-low frame synchronization input; enables shift register when low, sampled on SCLK falling edges. |
| 10 | SCLK | input | Serial clock input accepting frequencies up to 50MHz; data clocked on falling edges. |
| 11 | DIN | input | Serial data input sampled on SCLK falling edges; MSB transmitted first in 24-bit frame. |
| 12 | IOVDD | power_in | Digital input-output power supply, operating range 1.8V to 5.5V. |
| 13 | RST | input | Asynchronous active-low reset; resets all DAC outputs to zero-scale or midscale per RSTSEL. |
| 14 | RSTSEL | input | Reset select input; low selects zero-scale/binary mode, high selects midscale/two's complement. |
| 15 | ENABLE | input | Active-low enable control input; HIGH disables SPI interface. |
| 16 | LDAC | input | Load DACs rising-edge triggered input; synchronously updates all DAC outputs from buffers. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC8565ICPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac8565icpwr-etched.step/dac8565icpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8565icpwr.step/dac8565icpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
41885742ee83df2e, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).