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DAC8565IAPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC8565IAPWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC8565IAPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A. |
| 2 | VOUTB | output | Analog output voltage from DAC B. |
| 3 | VREFH/VREFOUT | bidirectional | Positive reference input or 2.5V reference output when internal reference is used; sources up to 20mA. |
| 4 | AVDD | power_in | Power-supply input, 2.7V to 5.5V. |
| 5 | VREFL | input | Negative reference input, 0V to AVDD/2V. |
| 6 | GND | power_in | Ground reference point. |
| 7 | VOUTC | output | Analog output voltage from DAC C. |
| 8 | VOUTD | output | Analog output voltage from DAC D. |
| 9 | SYNC | input | Active-low frame synchronization input with Schmitt-Trigger logic; enables shift register when low, acts as interrupt if raised before 24th SCLK edge. |
| 10 | SCLK | input | Serial clock input with Schmitt-Trigger logic; data transferred on falling edges at rates up to 50MHz. |
| 11 | DIN | input | Serial data input with Schmitt-Trigger logic clocked into 24-bit shift register on falling SCLK edges. |
| 12 | IOVDD | power_in | Digital input-output power supply, 1.8V to 5.5V. |
| 13 | RST | input | Asynchronous active-low reset input resetting all DAC channels to zero-scale or midscale per RSTSEL state. |
| 14 | RSTSEL | input | Reset select input determining reset destination (zero-scale if low, midscale if high) and input coding mode (binary if low, two's complement if high). |
| 15 | ENABLE | input | Active-low control input enabling the SPI interface. |
| 16 | LDAC | input | Rising edge-triggered load input updating all DAC output registers simultaneously. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC8565IAPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac8565iapwr-etched.step/dac8565iapwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8565iapwr.step/dac8565iapwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
41885742ee83df2e, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).