component
DAC8564IAPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# DAC8564IAPWR++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16++DAC8564IAPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUTA | output | DAC A analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |+| 2 | VOUTB | output | DAC B analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |+| 3 | VREFH/VREFOUT | bidirectional | Positive reference input when external reference is used or 2.5V internal reference output when internal reference is enabled; tri-states when internal reference is disabled; provides up to 20mA sourcing current. |+| 4 | AVDD | power_in | Analog power supply input, operating range 2.7V to 5.5V. |+| 5 | VREFL | input | Negative reference input with constraint VREFL < VREFH and AVDD - (VREFH + VREFL)/2 > 1.2V; input impedance 31kΩ. |+| 6 | GND | power_in | Ground reference point for all analog and digital circuits on this component. |+| 7 | VOUTC | output | DAC C analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |+| 8 | VOUTD | output | DAC D analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |+| 9 | SYNC | input | Level-triggered control input (active low) for frame synchronization; rising edge before 24th SCLK falling edge cancels write sequence; Schmitt trigger logic input. |+| 10 | SCLK | input | Serial clock input with maximum frequency 50MHz at IOVDD/AVDD = 3.6-5.5V or 25MHz at 2.7-3.6V; Schmitt trigger logic input. |+| 11 | DIN | input | Serial data input sampled at each SCLK falling edge into 24-bit input shift register; Schmitt trigger logic input. |+| 12 | IOVDD | power_in | Digital input-output power supply, operating range 1.8V to 5.5V. |+| 13 | A0 | input | Address select pin 0; must match DB22 data bit for proper device addressing on shared SPI bus. |+| 14 | A1 | input | Address select pin 1; must match DB23 data bit for proper device addressing on shared SPI bus. |+| 15 | ENABLE | input | Serial interface enable pin (active low); device stops listening to serial port when driven high. |+| 16 | LDAC | input | Load DAC register pin (rising edge triggered); simultaneously updates all four DAC outputs from their data buffers. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `DAC8564IAPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `dac8564iapwr-etched.step` / `dac8564iapwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8564iapwr.step` / `dac8564iapwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8564) (52 pp, sha256 `528d3c75fc813f22`, retrieved 2026-09-24, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac8564iapwr-datasheet.pdf)
page.jsonadded+189@@ -0,0 +1,189 @@+{+ "slug": "dac8564iapwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac8564iapwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac8564iapwr.kicad_sym",+ "dac8564iapwr.kicad_mod",+ "dac8564iapwr.glb",+ "dac8564iapwr.step",+ "dac8564iapwr.lbr",+ "docs/hero.png",+ "docs/dac8564iapwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DAC8564IAPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac8564",+ "parts": {+ "symbol": "dac8564iapwr.kicad_sym",+ "footprint": "dac8564iapwr.kicad_mod",+ "model_3d": "dac8564iapwr-etched.glb",+ "model_3d_plain": "dac8564iapwr.glb",+ "model_3d_step": "dac8564iapwr-etched.step",+ "model_3d_step_plain": "dac8564iapwr.step",+ "lbr": "dac8564iapwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2680186"+ },+ "pins": [+ {+ "number": "1",+ "name": "VOUTA",+ "type": "output",+ "description": "DAC A analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability."+ },+ {+ "number": "2",+ "name": "VOUTB",+ "type": "output",+ "description": "DAC B analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability."+ },+ {+ "number": "3",+ "name": "VREFH/VREFOUT",+ "type": "bidirectional",+ "description": "Positive reference input when external reference is used or 2.5V internal reference output when internal reference is enabled; tri-states when internal reference is disabled; provides up to 20mA sourcing current."+ },+ {+ "number": "4",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply input, operating range 2.7V to 5.5V."+ },+ {+ "number": "5",+ "name": "VREFL",+ "type": "input",+ "description": "Negative reference input with constraint VREFL < VREFH and AVDD - (VREFH + VREFL)/2 > 1.2V; input impedance 31kΩ."+ },+ {+ "number": "6",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference point for all analog and digital circuits on this component."+ },+ {+ "number": "7",+ "name": "VOUTC",+ "type": "output",+ "description": "DAC C analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability."+ },+ {+ "number": "8",+ "name": "VOUTD",+ "type": "output",+ "description": "DAC D analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability."+ },+ {+ "number": "9",+ "name": "SYNC",+ "type": "input",+ "description": "Level-triggered control input (active low) for frame synchronization; rising edge before 24th SCLK falling edge cancels write sequence; Schmitt trigger logic input."+ },+ {+ "number": "10",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input with maximum frequency 50MHz at IOVDD/AVDD = 3.6-5.5V or 25MHz at 2.7-3.6V; Schmitt trigger logic input."+ },+ {+ "number": "11",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input sampled at each SCLK falling edge into 24-bit input shift register; Schmitt trigger logic input."+ },+ {+ "number": "12",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Digital input-output power supply, operating range 1.8V to 5.5V."+ },+ {+ "number": "13",+ "name": "A0",+ "type": "input",+ "description": "Address select pin 0; must match DB22 data bit for proper device addressing on shared SPI bus."+ },+ {+ "number": "14",+ "name": "A1",+ "type": "input",+ "description": "Address select pin 1; must match DB23 data bit for proper device addressing on shared SPI bus."+ },+ {+ "number": "15",+ "name": "ENABLE",+ "type": "input",+ "description": "Serial interface enable pin (active low); device stops listening to serial port when driven high."+ },+ {+ "number": "16",+ "name": "LDAC",+ "type": "input",+ "description": "Load DAC register pin (rising edge triggered); simultaneously updates all four DAC outputs from their data buffers."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 52,+ "cost_usd": 0.5584,+ "at": "2026-09-24T06:15:51"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac8564",+ "pages": 52,+ "sha256": "528d3c75fc813f22",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}