component
DAC8564IAPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC8564IAPWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC8564IAPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | DAC A analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |
| 2 | VOUTB | output | DAC B analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |
| 3 | VREFH/VREFOUT | bidirectional | Positive reference input when external reference is used or 2.5V internal reference output when internal reference is enabled; tri-states when internal reference is disabled; provides up to 20mA sourcing current. |
| 4 | AVDD | power_in | Analog power supply input, operating range 2.7V to 5.5V. |
| 5 | VREFL | input | Negative reference input with constraint VREFL < VREFH and AVDD - (VREFH + VREFL)/2 > 1.2V; input impedance 31kΩ. |
| 6 | GND | power_in | Ground reference point for all analog and digital circuits on this component. |
| 7 | VOUTC | output | DAC C analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |
| 8 | VOUTD | output | DAC D analog output voltage, 0 to VREF range with output impedance 1Ω and ±20mA source/sink capability. |
| 9 | SYNC | input | Level-triggered control input (active low) for frame synchronization; rising edge before 24th SCLK falling edge cancels write sequence; Schmitt trigger logic input. |
| 10 | SCLK | input | Serial clock input with maximum frequency 50MHz at IOVDD/AVDD = 3.6-5.5V or 25MHz at 2.7-3.6V; Schmitt trigger logic input. |
| 11 | DIN | input | Serial data input sampled at each SCLK falling edge into 24-bit input shift register; Schmitt trigger logic input. |
| 12 | IOVDD | power_in | Digital input-output power supply, operating range 1.8V to 5.5V. |
| 13 | A0 | input | Address select pin 0; must match DB22 data bit for proper device addressing on shared SPI bus. |
| 14 | A1 | input | Address select pin 1; must match DB23 data bit for proper device addressing on shared SPI bus. |
| 15 | ENABLE | input | Serial interface enable pin (active low); device stops listening to serial port when driven high. |
| 16 | LDAC | input | Load DAC register pin (rising edge triggered); simultaneously updates all four DAC outputs from their data buffers. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC8564IAPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac8564iapwr-etched.step/dac8564iapwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8564iapwr.step/dac8564iapwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
528d3c75fc813f22, retrieved 2026-09-24, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).