# DAC8564IAPW

**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16

DAC8564IAPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A, with an output range of 0 to VREF V. |
| 2 | VOUTB | output | Analog output voltage from DAC B, with an output range of 0 to VREF V. |
| 3 | VREFH/VREFOUT | bidirectional | Positive reference input or reference output; 2.5V if the internal reference is used. |
| 4 | AVDD | power_in | Power-supply input, 2.7V to 5.5V. |
| 5 | VREFL | input | Negative reference input; the reference input range requires VREFL < VREFH and AVDD - (VREFH + VREFL)/2 > 1.2V. |
| 6 | GND | power_in | Ground reference point for all circuitry on the part. |
| 7 | VOUTC | output | Analog output voltage from DAC C, with an output range of 0 to VREF V. |
| 8 | VOUTD | output | Analog output voltage from DAC D, with an output range of 0 to VREF V. |
| 9 | SYNC | input | Level-triggered active-low frame sync input; data are sampled on falling SCLK edges and the DAC output updates after the 24th clock, and a SYNC rising edge before the 24th clock aborts the write. |
| 10 | SCLK | input | Serial clock input, Schmitt-trigger logic input, with data transfer rates up to 50MHz. |
| 11 | DIN | input | Serial data input, clocked into the 24-bit input shift register on each falling edge of the serial clock; Schmitt-trigger logic input. |
| 12 | IOVDD | power_in | Digital input-output power supply; the electrical characteristics specify IOVDD from 1.8V to 5.5V. |
| 13 | A0 | input | Address 0 input that sets the device address; see Table 5 of the datasheet. |
| 14 | A1 | input | Address 1 input that sets the device address; see Table 5 of the datasheet. |
| 15 | ENABLE | input | Active-low enable pin that connects the SPI interface to the serial port. |
| 16 | LDAC | input | Load DACs input, rising-edge triggered, which loads all DAC registers. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy |  |  | 4 | 12 | LSB | Measured by the line passing through codes 485 and 64714; DAC8564A, DAC8564C | 3 |
| Differential nonlinearity |  |  | 0.5 | 1 | LSB | 16-bit monotonic | 3 |
| Offset error |  |  | 5 | 8 | mV |  | 3 |
| Full-scale error |  |  | 0.2 | 0.5 | % of FSR |  | 3 |
| Gain error |  |  | 0.05 | 0.2 | % of FSR |  | 3 |
| Gain temperature coefficient (AVDD = 5V) |  |  | 1 |  | ppm of FSR/°C | AVDD = 5V | 3 |
| Gain temperature coefficient (AVDD = 2.7V) |  |  | 2 |  | ppm of FSR/°C | AVDD = 2.7V | 3 |
| Offset error drift |  |  | 1 |  | µV/°C | Measured by the line passing through codes 485 and 64714 | 3 |
| Output voltage settling time |  |  | 8 | 10 | µs | To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ, 0pF < CL < 200pF | 3 |
| Slew rate |  |  | 2.2 |  | V/µs |  | 3 |
| Code change glitch impulse |  |  | 0.15 |  | nV-s | 1LSB change around major carry | 3 |
| Digital feedthrough |  |  | 0.15 |  | nV-s | SCLK toggling, SYNC high | 3 |
| Channel-to-channel dc crosstalk |  |  | 0.25 |  | LSB | Full-scale swing on adjacent channel | 3 |
| Channel-to-channel ac crosstalk |  |  | -100 |  | dB | 1kHz full-scale sine wave, outputs unloaded | 3 |
| DC output impedance |  |  | 1 |  | Ω | At mid-code input | 3 |
| Short-circuit current |  |  | 50 |  | mA |  | 3 |
| Power-up time (AVDD = 5V) |  |  | 2.5 |  | µs | Coming out of power-down mode, AVDD = 5V | 3 |
| Power-up time (AVDD = 3V) |  |  | 5 |  | µs | Coming out of power-down mode, AVDD = 3V | 3 |
| SNR |  |  | 90 |  | dB |  | 3 |
| THD |  |  | -77 |  | dB | TA = +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz | 3 |
| SFDR |  |  | 78 |  | dB | First 19 harmonics removed for SNR calculation | 3 |
| SINAD |  |  | 77 |  | dB |  | 3 |
| DAC output noise density |  |  | 120 |  | nV/√Hz | TA = +25°C, at mid-code input, fOUT = 1kHz | 3 |
| DAC output noise |  |  | 6 |  | µVPP | TA = +25°C, at mid-code input, 0.1Hz to 10Hz | 3 |
| Internal reference current consumption (AVDD = 5.5V) |  |  | 360 |  | µA | AVDD = 5.5V | 3 |
| Internal reference current consumption (AVDD = 3.6V) |  |  | 348 |  | µA | AVDD = 3.6V | 3 |
| External reference current |  |  | 80 |  | µA | External VREF = 2.5V, if internal reference is disabled, all four channels active | 3 |
| Reference input impedance |  |  | 31 |  | kΩ |  | 3 |
| Reference output voltage |  | 2.4975 | 2.5 | 2.5025 | V | TA = +25°C | 4 |
| Initial accuracy |  | -0.1 | 0.004 | 0.1 | % | TA = +25°C | 4 |
| Output voltage temperature drift (DAC8564A, DAC8564B) |  |  | 5 | 25 | ppm/°C | Reference trimmed and tested at room temperature, characterized from -40°C to +120°C | 4 |
| Output voltage noise |  |  | 12 |  | µVPP | f = 0.1Hz to 10Hz | 4 |
| Load regulation, sourcing |  |  | 30 |  | µV/mA | TA = +25°C | 4 |
| Load regulation, sinking |  |  | 15 |  | µV/mA | TA = +25°C | 4 |
| Output current load capability |  | -20 |  | 20 | mA |  | 4 |
| Line regulation |  |  | 10 |  | µV/V | TA = +25°C | 4 |
| Long-term stability/drift (aging) |  |  | 50 |  | ppm | TA = +25°C, time = 0 to 1900 hours | 4 |
| Thermal hysteresis (first cycle) |  |  | 100 |  | ppm | First cycle | 4 |
| Thermal hysteresis (additional cycles) |  |  | 25 |  | ppm | Additional cycles | 4 |
| Input current |  | -1 |  | 1 | µA |  | 4 |
| Pin capacitance |  |  | 3 |  | pF |  | 4 |
| AVDD supply range | AVDD | 2.7 |  | 5.5 | V |  | 4 |
| IOVDD supply range | IOVDD | 1.8 |  | 5.5 | V |  | 4 |
| Normal mode supply current (AVDD = IOVDD = 3.6V to 5.5V) | IDD |  | 1 | 1.6 | mA | VINH = IOVDD and VINL = GND | 4 |
| Normal mode supply current (AVDD = IOVDD = 2.7V to 3.6V) | IDD |  | 0.95 | 1.5 | mA | VINH = IOVDD and VINL = GND | 4 |
| All power-down modes supply current (AVDD = IOVDD = 3.6V to 5.5V) | IDD |  | 1.3 | 3.5 | µA | VINH = IOVDD and VINL = GND | 4 |
| All power-down modes supply current (AVDD = IOVDD = 2.7V to 3.6V) | IDD |  | 0.5 | 2.5 | µA | VINH = IOVDD and VINL = GND | 4 |
| Normal mode power dissipation (AVDD = IOVDD = 3.6V to 5.5V) |  |  | 3.6 | 8.8 | mW | VINH = IOVDD and VINL = GND | 4 |
| Normal mode power dissipation (AVDD = IOVDD = 2.7V to 3.6V) |  |  | 2.6 | 5.4 | mW | VINH = IOVDD and VINL = GND | 4 |
| All power-down modes power dissipation (AVDD = IOVDD = 3.6V to 5.5V) |  |  | 4.7 | 19 | µW | VINH = IOVDD and VINL = GND | 4 |
| All power-down modes power dissipation (AVDD = IOVDD = 2.7V to 3.6V) |  |  | 1.4 | 9 | µW | VINH = IOVDD and VINL = GND | 4 |
| Specified performance temperature range |  | -40 |  | 105 | °C |  | 4 |
| AVDD to GND | AVDD | -0.3 |  | 6 | V | Over operating free-air temperature range | 2 |
| Operating temperature range |  | -40 |  | 125 | °C | Over operating free-air temperature range | 2 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 2 |
| Junction temperature range (TJ max) | TJ |  |  | 150 | °C |  | 2 |
| Thermal impedance, junction-to-ambient | θJA |  | 118 |  | °C/W |  | 2 |
| Thermal impedance, junction-to-case | θJC |  | 29 |  | °C/W |  | 2 |
| ESD rating, human body model (HBM) |  |  |  | 4000 | V |  | 2 |
| ESD rating, charged device model (CDM) |  |  |  | 1500 | V |  | 2 |

## CAD (KiCad official)

- Symbol: `DAC8564IAPW`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `dac8564iapw-etched.step` / `dac8564iapw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8564iapw.step` / `dac8564iapw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac8564.pdf) (53 pp, sha256 `8e7c7ad39fb9fc6f`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dac8564iapw-datasheet.pdf)