component
DAC8563SDSCR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
DAC8563SDSCR
Texas Instruments · Digital To Analog Converters (DACs) · WSON-10-EP(3x3)
DAC8563SDSCR from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output from DAC-A with rail-to-rail output buffer operation. |
| 2 | VOUTB | output | Analog output from DAC-B with rail-to-rail output buffer operation. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative edge-triggered timing signal for simultaneous DAC updates in asynchronous mode; must be connected to GND permanently in synchronous mode. |
| 5 | CLR | input | Falling-edge sensitive asynchronous clear input that loads mid-scale to all input and DAC registers for DAC8563. |
| 6 | SYNC | input | Active-low frame synchronization input that enables the shift register; rising edge before 23rd clock edge interrupts write sequence. |
| 7 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic. |
| 8 | DIN | input | Serial data input with Schmitt-trigger logic clocked into 24-bit shift register on SCLK falling edges. |
| 9 | AVDD | power_in | Power-supply input operating from 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional reference pin that outputs 2.5 V with ±5 mV initial accuracy when internal reference is enabled or accepts external reference input (0 to AVDD). |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 11 |
CAD (KiCad official)
- Symbol:
DAC8563SDSCR - Footprint:
Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm - 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
dac8563sdscr-etched.step/dac8563sdscr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8563sdscr.step/dac8563sdscr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
3fbba20baac4cf7e, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC8563SDSCR
**Texas Instruments** · Digital To Analog Converters (DACs) · WSON-10-EP(3x3)
DAC8563SDSCR from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output from DAC-A with rail-to-rail output buffer operation. |
| 2 | VOUTB | output | Analog output from DAC-B with rail-to-rail output buffer operation. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative edge-triggered timing signal for simultaneous DAC updates in asynchronous mode; must be connected to GND permanently in synchronous mode. |
| 5 | CLR | input | Falling-edge sensitive asynchronous clear input that loads mid-scale to all input and DAC registers for DAC8563. |
| 6 | SYNC | input | Active-low frame synchronization input that enables the shift register; rising edge before 23rd clock edge interrupts write sequence. |
| 7 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic. |
| 8 | DIN | input | Serial data input with Schmitt-trigger logic clocked into 24-bit shift register on SCLK falling edges. |
| 9 | AVDD | power_in | Power-supply input operating from 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional reference pin that outputs 2.5 V with ±5 mV initial accuracy when internal reference is enabled or accepts external reference input (0 to AVDD). |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 11 |
## CAD (KiCad official)
- Symbol: `DAC8563SDSCR`
- Footprint: `Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm`
- 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `dac8563sdscr-etched.step` / `dac8563sdscr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8563sdscr.step` / `dac8563sdscr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8563) (63 pp, sha256 `3fbba20baac4cf7e`, retrieved 2026-10-03, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac8563sdscr-datasheet.pdf)