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DAC8563SDGSR
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Texas Instruments Digital To Analog Converters (DAC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DAC8563SDGSR
Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm
DAC8563SDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A with rail-to-rail operation from 0 V to AVDD. |
| 2 | VOUTB | output | Analog output voltage from DAC-B with rail-to-rail operation from 0 V to AVDD. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative edge-triggered input for asynchronous simultaneous DAC updates or tied to GND for synchronous mode operation. |
| 5 | CLR | input | Falling-edge sensitive asynchronous clear input loading mid-scale to all registers; device exits clear mode on 24th SCLK falling edge of next write. |
| 6 | SYNC | input | Level-triggered active-low frame synchronization input enabling the serial shift register; DAC output updates on 24th SCLK falling edge with Schmitt-trigger logic. |
| 7 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic. |
| 8 | DIN | input | Serial data input clocked into the 24-bit shift register on each SCLK falling edge with Schmitt-trigger logic. |
| 9 | AVDD | power_in | Power-supply input with operating range from 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; outputs 2.5-V with ±5-mV initial accuracy when internal reference is enabled, or accepts external reference input from 0 V to AVDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
DAC8563SDGSR - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
dac8563sdgsr-etched.step/dac8563sdgsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8563sdgsr.step/dac8563sdgsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
3fbba20baac4cf7e, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC8563SDGSR
**Texas Instruments** · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm
DAC8563SDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A with rail-to-rail operation from 0 V to AVDD. |
| 2 | VOUTB | output | Analog output voltage from DAC-B with rail-to-rail operation from 0 V to AVDD. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative edge-triggered input for asynchronous simultaneous DAC updates or tied to GND for synchronous mode operation. |
| 5 | CLR | input | Falling-edge sensitive asynchronous clear input loading mid-scale to all registers; device exits clear mode on 24th SCLK falling edge of next write. |
| 6 | SYNC | input | Level-triggered active-low frame synchronization input enabling the serial shift register; DAC output updates on 24th SCLK falling edge with Schmitt-trigger logic. |
| 7 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic. |
| 8 | DIN | input | Serial data input clocked into the 24-bit shift register on each SCLK falling edge with Schmitt-trigger logic. |
| 9 | AVDD | power_in | Power-supply input with operating range from 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; outputs 2.5-V with ±5-mV initial accuracy when internal reference is enabled, or accepts external reference input from 0 V to AVDD. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |
## CAD (KiCad official)
- Symbol: `DAC8563SDGSR`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `dac8563sdgsr-etched.step` / `dac8563sdgsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8563sdgsr.step` / `dac8563sdgsr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8563) (63 pp, sha256 `3fbba20baac4cf7e`, retrieved 2026-10-03, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac8563sdgsr-datasheet.pdf)