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DAC8541Y

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Texas Instruments Digital To Analog Converters (DACs), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified DAC8541Y

by Ray · last 30 Oct 2026 · 1 record · files match
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30 Oct 2026RayPublished by the parts factory: tier mfr, 32 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC8541Y · TQFP-32(5x5) · 32 pins
  • ✓copper: 32 copper pads, none touching another net
  • ✓datasheet: all 32 pin names found in the 24-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TQFP-32_5x5mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ixeid90f/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 32 pins = 32 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 32 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
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Contents

README

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DAC8541Y

Texas Instruments · Digital To Analog Converters (DACs) · TQFP-32(5x5)

DAC8541Y from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB15 bidirectional Data input/output bit 15 (MSB) of the 16-bit parallel interface.
2 DB14 bidirectional Data input/output bit 14 of the 16-bit parallel interface.
3 DB13 bidirectional Data input/output bit 13 of the 16-bit parallel interface.
4 DB12 bidirectional Data input/output bit 12 of the 16-bit parallel interface.
5 DB11 bidirectional Data input/output bit 11 of the 16-bit parallel interface.
6 DB10 bidirectional Data input/output bit 10 of the 16-bit parallel interface.
7 DB9 bidirectional Data input/output bit 9 of the 16-bit parallel interface.
8 DB8 bidirectional Data input/output bit 8 of the 16-bit parallel interface.
9 DB7 bidirectional Data input/output bit 7 of the 16-bit parallel interface.
10 DB6 bidirectional Data input/output bit 6 of the 16-bit parallel interface.
11 DB5 bidirectional Data input/output bit 5 of the 16-bit parallel interface.
12 DB4 bidirectional Data input/output bit 4 of the 16-bit parallel interface.
13 DB3 bidirectional Data input/output bit 3 of the 16-bit parallel interface.
14 DB2 bidirectional Data input/output bit 2 of the 16-bit parallel interface.
15 DB1 bidirectional Data input/output bit 1 of the 16-bit parallel interface.
16 DB0 bidirectional Data input/output bit 0 (LSB) of the 16-bit parallel interface.
17 DGND power_in Digital ground.
18 DVDD power_in Digital supply input, 1.8 V to 5.5 V, which sets the digital I/O thresholds.
19 AVDD power_in Analog power supply input, 2.7 V to 5.5 V.
20 VREFH input Positive reference voltage input, referenced to AGND, with VREFH greater than VREFL and range 0 to AVDD.
21 VREFL input Negative reference voltage input, referenced to AGND and nominally AGND, with an acceptable range of −100 mV to 100 mV.
22 AGND power_in Analog ground.
23 VOUTSense input Analog output sense, the feedback terminal of the output amplifier.
24 VOUT output Analog output voltage from the DAC, with rail-to-rail output amplifier operation.
25 PD0 input Powerdown control bit 0.
26 PD1 input Powerdown control bit 1.
27 BTC/USB input Data input format select: high selects binary two's complement, low selects unipolar straight binary.
28 RSTSEL input Selects reset of VOUT to min-scale (low) or mid-scale (high) on an active RST.
29 RST input Rising edge resets VOUT to min-scale or mid-scale and does not reset input register data.
30 LDAC input Asynchronous load command; a rising edge transfers input register data to the DAC register.
31 R/W input Read/Write control input.
32 CS input Chip select, active low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(5x5)
Category Data Converters
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AGND -0.3 6 V 2
DVDD to DGND -0.3 6 V 2
Digital input voltage to DGND -0.3 V max is DVDD + 0.3 V 2
VOUT to AGND -0.3 V max is AVDD + 0.3 V 2
Operating temperature range -40 85 °C 2
Storage temperature range Tstg -65 150 °C 2
Junction temperature, TJ max TJ 150 °C 2
Relative accuracy -0.098 0.098 %FSR 2
Differential nonlinearity -1 1 LSB 16-Bit monotonic 2
Zero code error 5 20 mV All zeroes loaded to DAC register 2
Full-scale error -0.15 -0.8 %FSR All ones loaded to DAC register 2
Gain error -0.8 0.8 %FSR 2
Zero code error drift -20 20 µV/°C 2
Gain temperature coefficient -5 5 ppm of FSR/°C 2
Output voltage settling time (full scale) 8 10 µs RL = 2 kΩ; 0 pF < CL < 200 pF 2
Reference current (AVDD=VREFH=5 V) 50 75 µA AVDD = VREFH = 5 V, VREFL = AGND 3
Reference current (AVDD=VREFH=3.6 V) 35 60 µA AVDD = VREFH = 3.6 V, VREFL = AGND 3
VREFH input range 0 V VREFH>VREFL; max is AVDD 3
VREFL input range -100 100 mV 3
Input current -1 1 µA 3
DVDD supply voltage DVDD 1.8 5.5 V 3
DIDD digital supply current DIDD 0.2 1 µA DAC active and excluding load current, VIH = DVDD and VIL = DGND 3
AVDD supply voltage AVDD 2.7 5.5 V 3
AIDD normal operation (AVDD = 3.6 V to 5.5 V) AIDD 250 400 µA DAC active and excluding load current, AVDD = 3.6 V to 5.5 V, VIH = DVDD and VIL = DGND 3
AIDD normal operation (AVDD = 2.7 V to 3.6 V) AIDD 240 390 µA AVDD = 2.7 V to 3.6 V, VIH = DVDD and VIL = DGND 3
AIDD all power-down modes (AVDD = 3.6 V to 5.5 V) AIDD 0.2 1 µA AVDD = 3.6 V to 5.5 V, VIH = DVDD and VIL = DGND 3
AIDD all power-down modes (AVDD = 2.7 V to 3.6 V) AIDD 0.05 1 µA AVDD = 2.7 V to 3.6 V, VIH = DVDD and VIL = DGND 3
Pulse width: CS low for valid write tw1 20 ns 5
Setup time: R/W low before CS falling tsu1 0 ns see Note 4 5
Setup time: data in valid before CS falling tsu2 0 ns 5
Hold time: R/W low after CS rising th1 10 ns see Note 4 5
Hold time: data in valid after CS rising th2 15 ns 5
Pulse width: CS low for valid read tw2 40 ns 5
Setup time: R/W high before CS falling tsu3 30 ns 5
Delay time: data out valid after CS falling td1 60 80 ns 5
Hold time: R/W high after CS rising th3 10 ns 5
Hold time: data out valid after CS rising th4 5 20 ns 5
Setup time: LDAC rising after CS falling tsu4 10 ns see Note 4 5
Delay time: CS low after LDAC rising td2 50 ns 5
Pulse width: LDAC low tw3 40 ns 5
Pulse width: LDAC high tw4 40 ns 5
Pulse width: CS high tw5 80 ns see Note 4 5
Setup time: RSTSEL valid before RST rising tsu5 0 ns 5
Hold time: RSTSEL valid after RST rising th5 20 ns 5
Pulse width: RST low tw6 40 ns 5
Pulse width: RST high tw7 40 ns 5

CAD (KiCad official)

  • Symbol: DAC8541Y
  • Footprint: Package_QFP:TQFP-32_5x5mm_P0.5mm
  • 3D model: TQFP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: dac8541y-etched.step / dac8541y-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8541y.step / dac8541y.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 648c6041e15dab10, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF