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Initial commit: component/dac8168icpwr

Ray ·1f3dc4a57c ·8d ago
2 files changed +257
README.mdadded+53
@@ -0,0 +1,53 @@+# DAC8168ICPWR++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16++DAC8168ICPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LDAC | input | Load DACs; used for asynchronous and synchronous update control of DAC output registers. |+| 2 | SYNC | input | Level-triggered control input (active low); frame synchronization signal enabling input shift register when low. |+| 3 | AVDD | power_in | Power-supply input; operating voltage range 2.7V to 5.5V. |+| 4 | VOUTA | output | Analog output voltage from DAC A; output voltage range 0V to AVDD. |+| 5 | VOUTC | output | Analog output voltage from DAC C; output voltage range 0V to AVDD. |+| 6 | VOUTE | output | Analog output voltage from DAC E; output voltage range 0V to AVDD. |+| 7 | VOUTG | output | Analog output voltage from DAC G; output voltage range 0V to AVDD. |+| 8 | VREFIN/VREFOUT | bidirectional | Positive reference input/reference output; 2.5V internal reference (default disabled) or external reference input up to AVDD/2 for grade C. |+| 9 | CLR | input | Asynchronous clear input; falling edge triggered to clear all DAC registers and buffers; minimum pulse width 80ns. |+| 10 | VOUTH | output | Analog output voltage from DAC H; output voltage range 0V to AVDD. |+| 11 | VOUTF | output | Analog output voltage from DAC F; output voltage range 0V to AVDD. |+| 12 | VOUTD | output | Analog output voltage from DAC D; output voltage range 0V to AVDD. |+| 13 | VOUTB | output | Analog output voltage from DAC B; output voltage range 0V to AVDD. |+| 14 | GND | power_in | Ground reference point for all circuitry on the device. |+| 15 | DIN | input | Serial data input; data clocked into 32-bit shift register on each falling edge of SCLK; Schmitt-trigger logic input. |+| 16 | SCLK | input | Serial clock input; maximum data transfer rate 50MHz; Schmitt-trigger logic input. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `DAC8168ICPWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `dac8168icpwr-etched.step` / `dac8168icpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8168icpwr.step` / `dac8168icpwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac7568) (72 pp, sha256 `e14f8beb0a8c704b`, retrieved 2026-09-27, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac8168icpwr-datasheet.pdf)
page.jsonadded+204
@@ -0,0 +1,204 @@+{+  "slug": "dac8168icpwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "dac8168icpwr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "dac8168icpwr.kicad_sym",+    "dac8168icpwr.kicad_mod",+    "dac8168icpwr.glb",+    "dac8168icpwr.step",+    "dac8168icpwr.lbr",+    "docs/hero.png",+    "docs/dac8168icpwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "DAC8168ICPWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-16",+    "pin_count": 16,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/dac7568",+    "parts": {+      "symbol": "dac8168icpwr.kicad_sym",+      "footprint": "dac8168icpwr.kicad_mod",+      "model_3d": "dac8168icpwr-etched.glb",+      "model_3d_plain": "dac8168icpwr.glb",+      "model_3d_step": "dac8168icpwr-etched.step",+      "model_3d_step_plain": "dac8168icpwr.step",+      "lbr": "dac8168icpwr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2679992",+      "digikey": "DAC8168ICPWR-ND",+      "mouser": "595-DAC8168ICPWR"+    },+    "distributor_check": {+      "checked_at": "2026-09-27T10:18:12Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "DAC8168ICPWR-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-DAC8168ICPWR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "LDAC",+        "type": "input",+        "description": "Load DACs; used for asynchronous and synchronous update control of DAC output registers."+      },+      {+        "number": "2",+        "name": "SYNC",+        "type": "input",+        "description": "Level-triggered control input (active low); frame synchronization signal enabling input shift register when low."+      },+      {+        "number": "3",+        "name": "AVDD",+        "type": "power_in",+        "description": "Power-supply input; operating voltage range 2.7V to 5.5V."+      },+      {+        "number": "4",+        "name": "VOUTA",+        "type": "output",+        "description": "Analog output voltage from DAC A; output voltage range 0V to AVDD."+      },+      {+        "number": "5",+        "name": "VOUTC",+        "type": "output",+        "description": "Analog output voltage from DAC C; output voltage range 0V to AVDD."+      },+      {+        "number": "6",+        "name": "VOUTE",+        "type": "output",+        "description": "Analog output voltage from DAC E; output voltage range 0V to AVDD."+      },+      {+        "number": "7",+        "name": "VOUTG",+        "type": "output",+        "description": "Analog output voltage from DAC G; output voltage range 0V to AVDD."+      },+      {+        "number": "8",+        "name": "VREFIN/VREFOUT",+        "type": "bidirectional",+        "description": "Positive reference input/reference output; 2.5V internal reference (default disabled) or external reference input up to AVDD/2 for grade C."+      },+      {+        "number": "9",+        "name": "CLR",+        "type": "input",+        "description": "Asynchronous clear input; falling edge triggered to clear all DAC registers and buffers; minimum pulse width 80ns."+      },+      {+        "number": "10",+        "name": "VOUTH",+        "type": "output",+        "description": "Analog output voltage from DAC H; output voltage range 0V to AVDD."+      },+      {+        "number": "11",+        "name": "VOUTF",+        "type": "output",+        "description": "Analog output voltage from DAC F; output voltage range 0V to AVDD."+      },+      {+        "number": "12",+        "name": "VOUTD",+        "type": "output",+        "description": "Analog output voltage from DAC D; output voltage range 0V to AVDD."+      },+      {+        "number": "13",+        "name": "VOUTB",+        "type": "output",+        "description": "Analog output voltage from DAC B; output voltage range 0V to AVDD."+      },+      {+        "number": "14",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference point for all circuitry on the device."+      },+      {+        "number": "15",+        "name": "DIN",+        "type": "input",+        "description": "Serial data input; data clocked into 32-bit shift register on each falling edge of SCLK; Schmitt-trigger logic input."+      },+      {+        "number": "16",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock input; maximum data transfer rate 50MHz; Schmitt-trigger logic input."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 72,+        "cost_usd": 0.5777,+        "at": "2026-09-27T10:17:53"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/dac7568",+        "pages": 72,+        "sha256": "e14f8beb0a8c704b",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file