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docs dac8165idpw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers dac8165idpw: viewers · Ray
dac8165idpw-etched.fit.json dac8165idpw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dac8165idpw-etched.glb dac8165idpw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dac8165idpw-etched.step dac8165idpw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dac8165idpw.glb Publish 0.1.0 · Ray
dac8165idpw.kicad_mod Publish 0.1.0 · Ray
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dac8165idpw.lbr Publish 0.1.0 · Ray
dac8165idpw.step Publish 0.1.0 · Ray
package.json dac8165idpw: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json dac8165idpw: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/dac8165idpw · Ray

DAC8165IDPW

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16

DAC8165IDPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A.
2 VOUTB output Analog output voltage from DAC B.
3 VREFH/VREFOUT bidirectional Positive reference input or 2.5V reference output when internal reference is used; high-impedance when disabled.
4 AVDD power_in Analog power supply input, 2.7V to 5.5V.
5 VREFL input Negative reference input.
6 GND power_in Ground reference point for all circuitry.
7 VOUTC output Analog output voltage from DAC C.
8 VOUTD output Analog output voltage from DAC D.
9 SYNC input Level-triggered frame synchronization control input (active low); rising edge before 24th clock acts as interrupt.
10 SCLK input Serial clock input with Schmitt-trigger logic, up to 50MHz.
11 DIN input Serial data input with Schmitt-trigger logic; data clocked on falling edge of SCLK.
12 IOVDD power_in Digital input-output power supply.
13 RST input Asynchronous reset (active low); resets all DAC channels to zero-scale or mid-scale based on RSTSEL.
14 RSTSEL input Reset select; low = zero-scale, high = mid-scale reset state.
15 ENABLE input Enable pin (active low) that connects the SPI interface to the serial port.
16 LDAC input Load DACs; rising edge triggered to load all DAC registers simultaneously.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Acquisition
Pins 16

CAD (KiCad official)

  • Symbol: DAC8165IDPW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: dac8165idpw-etched.step / dac8165idpw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac8165idpw.step / dac8165idpw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (51 pp, sha256 af33975ce1ea1a5c, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF