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DAC8164IAPW
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DAC8164IAPW
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC8164IAPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A. |
| 2 | VOUTB | output | Analog output voltage from DAC B. |
| 3 | VREFH/VREFOUT | bidirectional | Positive reference input / reference output, 2.5V if internal reference is used. |
| 4 | AVDD | power_in | Power-supply input, 2.7V to 5.5V. |
| 5 | VREFL | input | Negative reference input. |
| 6 | GND | power_in | Ground reference point for all circuitry on the part. |
| 7 | VOUTC | output | Analog output voltage from DAC C. |
| 8 | VOUTD | output | Analog output voltage from DAC D. |
| 9 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC output updates following the 24th clock, and a SYNC rising edge before the 24th clock edge aborts the write sequence. Schmitt-Trigger logic input. |
| 10 | SCLK | input | Serial clock input with data transfer rates up to 50MHz. Schmitt-Trigger logic input. |
| 11 | DIN | input | Serial data input clocked into the 24-bit input shift register on each falling edge of SCLK. Schmitt-Trigger logic input. |
| 12 | IOVDD | power_in | Digital input-output power supply, 1.8V to 5.5V. |
| 13 | A0 | input | Address 0 input that sets the device address, see Table 5. |
| 14 | A1 | input | Address 1 input that sets the device address, see Table 5. |
| 15 | ENABLE | input | Active-low enable pin that connects the SPI interface to the serial port. |
| 16 | LDAC | input | Load DACs input; rising edge triggered, loads all DAC registers. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC8164IAPW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac8164iapw-etched.step/dac8164iapw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8164iapw.step/dac8164iapw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
88f4f8c93b7d3d63, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC8164IAPW
**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16
DAC8164IAPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A. |
| 2 | VOUTB | output | Analog output voltage from DAC B. |
| 3 | VREFH/VREFOUT | bidirectional | Positive reference input / reference output, 2.5V if internal reference is used. |
| 4 | AVDD | power_in | Power-supply input, 2.7V to 5.5V. |
| 5 | VREFL | input | Negative reference input. |
| 6 | GND | power_in | Ground reference point for all circuitry on the part. |
| 7 | VOUTC | output | Analog output voltage from DAC C. |
| 8 | VOUTD | output | Analog output voltage from DAC D. |
| 9 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC output updates following the 24th clock, and a SYNC rising edge before the 24th clock edge aborts the write sequence. Schmitt-Trigger logic input. |
| 10 | SCLK | input | Serial clock input with data transfer rates up to 50MHz. Schmitt-Trigger logic input. |
| 11 | DIN | input | Serial data input clocked into the 24-bit input shift register on each falling edge of SCLK. Schmitt-Trigger logic input. |
| 12 | IOVDD | power_in | Digital input-output power supply, 1.8V to 5.5V. |
| 13 | A0 | input | Address 0 input that sets the device address, see Table 5. |
| 14 | A1 | input | Address 1 input that sets the device address, see Table 5. |
| 15 | ENABLE | input | Active-low enable pin that connects the SPI interface to the serial port. |
| 16 | LDAC | input | Load DACs input; rising edge triggered, loads all DAC registers. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `DAC8164IAPW`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `dac8164iapw-etched.step` / `dac8164iapw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8164iapw.step` / `dac8164iapw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac8164.pdf) (51 pp, sha256 `88f4f8c93b7d3d63`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac8164iapw-datasheet.pdf)