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DAC8163SQDGSRQ1
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Texas Instruments Digital To Analog Converters (DACs), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DAC8163SQDGSRQ1
Texas Instruments · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm
DAC8163SQDGSRQ1 from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A. |
| 2 | VOUTB | output | Analog output voltage from DAC-B. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative edge-triggered LDAC input for simultaneous DAC updates in asynchronous mode; must be tied to GND or held low for synchronous updates. |
| 5 | CLR | input | Asynchronous falling-edge-sensitive clear input that loads mid-scale (DACxx63-Q1) to all input and DAC registers; exits clear mode on the 24th falling edge of the next write. |
| 6 | SYNC | input | Active-low frame synchronization input with Schmitt-trigger logic; enables the input shift register when low, and DAC output updates after the 24th clock falling edge. |
| 7 | SCLK | input | Serial clock input with Schmitt-trigger logic; data can be transferred at rates up to 50 MHz. |
| 8 | DIN | input | Serial data input with Schmitt-trigger logic; data are clocked into the 24-bit input shift register on each falling edge of SCLK. |
| 9 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; 2.5-V output if the internal reference is used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
DAC8163SQDGSRQ1 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
dac8163sqdgsrq1-etched.step/dac8163sqdgsrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac8163sqdgsrq1.step/dac8163sqdgsrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (56 pp, sha256
3dc6a01184f32593, retrieved 2026-11-02, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC8163SQDGSRQ1
**Texas Instruments** · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm
DAC8163SQDGSRQ1 from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A. |
| 2 | VOUTB | output | Analog output voltage from DAC-B. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative edge-triggered LDAC input for simultaneous DAC updates in asynchronous mode; must be tied to GND or held low for synchronous updates. |
| 5 | CLR | input | Asynchronous falling-edge-sensitive clear input that loads mid-scale (DACxx63-Q1) to all input and DAC registers; exits clear mode on the 24th falling edge of the next write. |
| 6 | SYNC | input | Active-low frame synchronization input with Schmitt-trigger logic; enables the input shift register when low, and DAC output updates after the 24th clock falling edge. |
| 7 | SCLK | input | Serial clock input with Schmitt-trigger logic; data can be transferred at rates up to 50 MHz. |
| 8 | DIN | input | Serial data input with Schmitt-trigger logic; data are clocked into the 24-bit input shift register on each falling edge of SCLK. |
| 9 | AVDD | power_in | Power-supply input, 2.7 V to 5.5 V. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin; 2.5-V output if the internal reference is used. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
## CAD (KiCad official)
- Symbol: `DAC8163SQDGSRQ1`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `dac8163sqdgsrq1-etched.step` / `dac8163sqdgsrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac8163sqdgsrq1.step` / `dac8163sqdgsrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8163-q1) (56 pp, sha256 `3dc6a01184f32593`, retrieved 2026-11-02, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac8163sqdgsrq1-datasheet.pdf)