component
DAC81401PWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
196f347
DAC81401PWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-20
DAC81401PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREFIO | bidirectional | Internal reference output or external reference input; connect a 150nF capacitor to ground. |
| 2 | VREFGND | input | Reference ground, connects to 0V. |
| 3 | AVSS | power_in | Negative power supply; AVSS to GND is specified from -21.5 V to 0 V. |
| 4 | NC | unconnected | Must be left unconnected, pin floating. |
| 5 | AVDD | power_in | Positive power supply; AVDD to GND is specified from 4.5 V to 41.5 V. |
| 6 | NC | unconnected | Must be left unconnected, pin floating. |
| 7 | CCOMP | input | External compensation capacitor connection for VOUT; a 470pF typical capacitor improves stability with capacitive loads up to 1μF at the cost of increased settling time. |
| 8 | NC | unconnected | Must be left unconnected, pin floating. |
| 9 | VOUT | output | DAC voltage output pin. |
| 10 | VSENSEP | input | Sense output pin for the positive voltage output load connection. |
| 11 | VSENSEN | input | Connect to 0V. |
| 12 | FAULT | output | Open-drain FAULT output that goes low when a fault condition is detected; requires an external 10kΩ pullup resistor. |
| 13 | SDO | output | Serial data output; data are valid on the rising or falling edge of SCLK as set by FSDO. |
| 14 | SCLK | input | Serial clock input of the SPI, supporting rates up to 50MHz, with Schmitt-trigger logic input. |
| 15 | SDIN | input | Serial data input; data are clocked into the register on the falling edge of the serial clock, with Schmitt-trigger logic input. |
| 16 | SYNC | input | SPI bus chip select input (active low); data bits are not clocked into the shift register unless SYNC is low, and SDO is Hi-Z when SYNC is high. |
| 17 | IOVDD | power_in | IO pin power supply, specified from 1.7 V to 5.5 V to GND. |
| 18 | NC | unconnected | Must be left unconnected, pin floating. |
| 19 | GND | power_in | Digital and analog ground, connects to 0V. |
| 20 | VDD | power_in | Digital and analog power supply, specified from 4.5 V to 5.5 V to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Data Acquisition |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | -0.3 | 6 | V | 4 | |||
| IOVDD to GND | -0.3 | 6 | V | 4 | |||
| AVDD to GND | -0.3 | 44 | V | 4 | |||
| AVSS to GND | -22 | 0.3 | V | 4 | |||
| AVDD to AVSS | -0.3 | 44 | V | 4 | |||
| VREFGND / VSENSEN to GND | -0.3 | 0.3 | V | 4 | |||
| FAULT to GND | -0.3 | 6 | V | 4 | |||
| Input current into any digital pin (SCLK, SDIN, SDO, SYNC) | -10 | 10 | mA | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -60 | 150 | °C | 4 | ||
| VDD to GND | 4.5 | 5.5 | V | 4 | |||
| IOVDD to GND | 1.7 | 5.5 | V | 4 | |||
| AVDD to GND | 4.5 | 41.5 | V | 4 | |||
| AVSS to GND | -21.5 | 0 | V | 4 | |||
| AVDD to AVSS | 4.5 | 43 | V | 4 | |||
| Operating ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Relative accuracy INL | INL | -1 | 0.4 | 1 | LSB | DAC81401, all ranges except 0V to 40V range | 5 |
| Relative accuracy INL | INL | -2 | 2 | LSB | DAC81401, 0V to 40V range | 5 | |
| Differential nonlinearity DNL | DNL | -1 | 0.3 | 1 | LSB | 5 | |
| Total unadjusted error TUE | TUE | -0.09 | 0.09 | %FSR | Unipolar ranges, AVSS = 0V | 5 | |
| Total unadjusted error TUE | TUE | -0.07 | 0.07 | %FSR | Unipolar ranges, AVSS = 0V, 0°C ≤ TA ≤ 50°C | 5 | |
| Total unadjusted error TUE | TUE | -0.095 | 0.095 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Offset error OE | OE | -0.05 | 0.05 | %FSR | Unipolar ranges, AVSS = 0V | 5 | |
| Offset error temperature coefficient OE-TC | OE-TC | -2 | 2 | ppmFSR/°C | Unipolar ranges, AVSS = 0V | 5 | |
| Zero-code (negative full scale) error ZCE | ZCE | 0.15 | %FSR | Unipolar ranges, AVSS = 0V | 5 | ||
| Zero-code (negative full scale) error ZCE | ZCE | 0.05 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | ||
| Full-scale error FSE | FSE | -0.08 | 0.08 | %FSR | Unipolar ranges, AVSS = 0V | 5 | |
| Full-scale error temperature coefficient FSE-TC | FSE-TC | -3 | 3 | ppmFSR/°C | 5 | ||
| Gain error GE | GE | -0.075 | 0.075 | %FSR | Unipolar ranges, AVSS = 0V | 5 | |
| Bipolar gain error BPGE | BPGE | -0.065 | 0.065 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Gain error temperature coefficient GE-TC | GE-TC | -2 | 2 | ppmFSR/°C | 5 | ||
| Bipolar zero (midscale) error BPZE | BPZE | -0.04 | 0.04 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Bipolar zero (midscale) error temperature coefficient BPZE-TC | BPZE-TC | -2 | 2 | ppmFSR/°C | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Output voltage | VOUT | 0 | 5 | V | 0V to 5V range | 6 | |
| Output voltage | VOUT | 0 | 6 | V | 20% overrange of 0V to 5V | 6 | |
| Output voltage | VOUT | 0 | 10 | V | 0V to 10V range | 6 | |
| Output voltage | VOUT | 0 | 12 | V | 20% overrange of 0V to 10V | 6 | |
| Output voltage | VOUT | 0 | 20 | V | 0V to 20V range | 6 | |
| Output voltage | VOUT | 0 | 24 | V | 20% overrange of 0V to 20V | 6 | |
| Output voltage | VOUT | 0 | 40 | V | 0V to 40V range | 6 | |
| Output voltage | VOUT | -5 | 5 | V | -5V to +5V range | 6 | |
| Output voltage | VOUT | -6 | 6 | V | 20% overrange of -5V to +5V | 6 | |
| Output voltage | VOUT | -10 | 10 | V | -10V to +10V range | 6 | |
| Output voltage | VOUT | -12 | 12 | V | 20% overrange of -10V to +10V | 6 | |
| Output voltage | VOUT | -20 | 20 | V | -20V to +20V range | 6 | |
| Output voltage headroom (to AVDD) and footroom (to AVSS) | 1.25 | V | -10mA ≤ load current ≤ 10mA | 6 | |||
| Output voltage headroom (to AVDD) and footroom (to AVSS) | 1.5 | V | 5.5V < AVDD ≤ 41.5V, −15mA ≤ load current ≤ +15mA | 6 | |||
| Short-circuit current IOS | IOS | 40 | mA | Full-scale output shorted to AVSS | 6 | ||
| Short-circuit current IOS | IOS | 25 | mA | Zero-scale output shorted to AVDD, 4.5V ≤ AVDD ≤ 5.5V | 6 | ||
| Load regulation | 50 | µV/mA | DAC at midscale, -15mA ≤ load current ≤ +15mA | 6 | |||
| Capacitive load CL | CL | 2 | nF | RLOAD = open, CCOMP pin left floating | 6 | ||
| Capacitive load CL | CL | 1 | µF | RLOAD = open, CCOMP pin = 470pF ±10% to VOUT | 6 | ||
| Junction-to-ambient thermal resistance RθJA | RθJA | 83.1 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-case (top) thermal resistance RθJC(top) | RθJC(top) | 21.7 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-board thermal resistance RθJB | RθJB | 36 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-board characterization parameter ΨJB | ΨJB | 35.4 | °C/W | PW (TSSOP) 20 pins | 5 |
CAD (KiCad official)
- Symbol:
DAC81401PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
dac81401pwr-etched.step/dac81401pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac81401pwr.step/dac81401pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
8d810beb78f170e9, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC81401PWR
**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-20
DAC81401PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREFIO | bidirectional | Internal reference output or external reference input; connect a 150nF capacitor to ground. |
| 2 | VREFGND | input | Reference ground, connects to 0V. |
| 3 | AVSS | power_in | Negative power supply; AVSS to GND is specified from -21.5 V to 0 V. |
| 4 | NC | unconnected | Must be left unconnected, pin floating. |
| 5 | AVDD | power_in | Positive power supply; AVDD to GND is specified from 4.5 V to 41.5 V. |
| 6 | NC | unconnected | Must be left unconnected, pin floating. |
| 7 | CCOMP | input | External compensation capacitor connection for VOUT; a 470pF typical capacitor improves stability with capacitive loads up to 1μF at the cost of increased settling time. |
| 8 | NC | unconnected | Must be left unconnected, pin floating. |
| 9 | VOUT | output | DAC voltage output pin. |
| 10 | VSENSEP | input | Sense output pin for the positive voltage output load connection. |
| 11 | VSENSEN | input | Connect to 0V. |
| 12 | FAULT | output | Open-drain FAULT output that goes low when a fault condition is detected; requires an external 10kΩ pullup resistor. |
| 13 | SDO | output | Serial data output; data are valid on the rising or falling edge of SCLK as set by FSDO. |
| 14 | SCLK | input | Serial clock input of the SPI, supporting rates up to 50MHz, with Schmitt-trigger logic input. |
| 15 | SDIN | input | Serial data input; data are clocked into the register on the falling edge of the serial clock, with Schmitt-trigger logic input. |
| 16 | SYNC | input | SPI bus chip select input (active low); data bits are not clocked into the shift register unless SYNC is low, and SDO is Hi-Z when SYNC is high. |
| 17 | IOVDD | power_in | IO pin power supply, specified from 1.7 V to 5.5 V to GND. |
| 18 | NC | unconnected | Must be left unconnected, pin floating. |
| 19 | GND | power_in | Digital and analog ground, connects to 0V. |
| 20 | VDD | power_in | Digital and analog power supply, specified from 4.5 V to 5.5 V to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Data Acquisition |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | | -0.3 | | 6 | V | | 4 |
| IOVDD to GND | | -0.3 | | 6 | V | | 4 |
| AVDD to GND | | -0.3 | | 44 | V | | 4 |
| AVSS to GND | | -22 | | 0.3 | V | | 4 |
| AVDD to AVSS | | -0.3 | | 44 | V | | 4 |
| VREFGND / VSENSEN to GND | | -0.3 | | 0.3 | V | | 4 |
| FAULT to GND | | -0.3 | | 6 | V | | 4 |
| Input current into any digital pin (SCLK, SDIN, SDO, SYNC) | | -10 | | 10 | mA | | 4 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -60 | | 150 | °C | | 4 |
| VDD to GND | | 4.5 | | 5.5 | V | | 4 |
| IOVDD to GND | | 1.7 | | 5.5 | V | | 4 |
| AVDD to GND | | 4.5 | | 41.5 | V | | 4 |
| AVSS to GND | | -21.5 | | 0 | V | | 4 |
| AVDD to AVSS | | 4.5 | | 43 | V | | 4 |
| Operating ambient temperature | TA | -40 | | 125 | °C | | 4 |
| Relative accuracy INL | INL | -1 | 0.4 | 1 | LSB | DAC81401, all ranges except 0V to 40V range | 5 |
| Relative accuracy INL | INL | -2 | | 2 | LSB | DAC81401, 0V to 40V range | 5 |
| Differential nonlinearity DNL | DNL | -1 | 0.3 | 1 | LSB | | 5 |
| Total unadjusted error TUE | TUE | -0.09 | | 0.09 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Total unadjusted error TUE | TUE | -0.07 | | 0.07 | %FSR | Unipolar ranges, AVSS = 0V, 0°C ≤ TA ≤ 50°C | 5 |
| Total unadjusted error TUE | TUE | -0.095 | | 0.095 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Offset error OE | OE | -0.05 | | 0.05 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Offset error temperature coefficient OE-TC | OE-TC | -2 | | 2 | ppmFSR/°C | Unipolar ranges, AVSS = 0V | 5 |
| Zero-code (negative full scale) error ZCE | ZCE | | | 0.15 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Zero-code (negative full scale) error ZCE | ZCE | | | 0.05 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Full-scale error FSE | FSE | -0.08 | | 0.08 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Full-scale error temperature coefficient FSE-TC | FSE-TC | -3 | | 3 | ppmFSR/°C | | 5 |
| Gain error GE | GE | -0.075 | | 0.075 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Bipolar gain error BPGE | BPGE | -0.065 | | 0.065 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Gain error temperature coefficient GE-TC | GE-TC | -2 | | 2 | ppmFSR/°C | | 5 |
| Bipolar zero (midscale) error BPZE | BPZE | -0.04 | | 0.04 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Bipolar zero (midscale) error temperature coefficient BPZE-TC | BPZE-TC | -2 | | 2 | ppmFSR/°C | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Output voltage | VOUT | 0 | | 5 | V | 0V to 5V range | 6 |
| Output voltage | VOUT | 0 | | 6 | V | 20% overrange of 0V to 5V | 6 |
| Output voltage | VOUT | 0 | | 10 | V | 0V to 10V range | 6 |
| Output voltage | VOUT | 0 | | 12 | V | 20% overrange of 0V to 10V | 6 |
| Output voltage | VOUT | 0 | | 20 | V | 0V to 20V range | 6 |
| Output voltage | VOUT | 0 | | 24 | V | 20% overrange of 0V to 20V | 6 |
| Output voltage | VOUT | 0 | | 40 | V | 0V to 40V range | 6 |
| Output voltage | VOUT | -5 | | 5 | V | -5V to +5V range | 6 |
| Output voltage | VOUT | -6 | | 6 | V | 20% overrange of -5V to +5V | 6 |
| Output voltage | VOUT | -10 | | 10 | V | -10V to +10V range | 6 |
| Output voltage | VOUT | -12 | | 12 | V | 20% overrange of -10V to +10V | 6 |
| Output voltage | VOUT | -20 | | 20 | V | -20V to +20V range | 6 |
| Output voltage headroom (to AVDD) and footroom (to AVSS) | | | | 1.25 | V | -10mA ≤ load current ≤ 10mA | 6 |
| Output voltage headroom (to AVDD) and footroom (to AVSS) | | | | 1.5 | V | 5.5V < AVDD ≤ 41.5V, −15mA ≤ load current ≤ +15mA | 6 |
| Short-circuit current IOS | IOS | | | 40 | mA | Full-scale output shorted to AVSS | 6 |
| Short-circuit current IOS | IOS | | | 25 | mA | Zero-scale output shorted to AVDD, 4.5V ≤ AVDD ≤ 5.5V | 6 |
| Load regulation | | | | 50 | µV/mA | DAC at midscale, -15mA ≤ load current ≤ +15mA | 6 |
| Capacitive load CL | CL | | | 2 | nF | RLOAD = open, CCOMP pin left floating | 6 |
| Capacitive load CL | CL | | | 1 | µF | RLOAD = open, CCOMP pin = 470pF ±10% to VOUT | 6 |
| Junction-to-ambient thermal resistance RθJA | RθJA | | 83.1 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | RθJC(top) | | 21.7 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-board thermal resistance RθJB | RθJB | | 36 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-board characterization parameter ΨJB | ΨJB | | 35.4 | | °C/W | PW (TSSOP) 20 pins | 5 |
## CAD (KiCad official)
- Symbol: `DAC81401PWR`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `dac81401pwr-etched.step` / `dac81401pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac81401pwr.step` / `dac81401pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac81401.pdf) (55 pp, sha256 `8d810beb78f170e9`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac81401pwr-datasheet.pdf)