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DAC80501ZDGST
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Texas Instruments Digital To Analog Converters (DAC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDAC80501ZDGST
Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm
DAC80501ZDGST from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Analog supply voltage, 2.7 V to 5.5 V. |
| 2 | VOUT | output | Analog output voltage from the DAC. |
| 3 | NC | unconnected | No connection; leave floating. |
| 4 | AGND | power_in | Ground reference point for all circuitry on the device. |
| 5 | SPI2C | input | Interface select pin: SPI mode when SPI2C = 0 and I2C mode when SPI2C = 1; it must be kept static after the device powers up. |
| 6 | SCLK/SCL | input | Serial interface clock for SPI or I2C mode. |
| 7 | SYNC/A0 | input | In SPI mode this active-low frame synchronization input enables the serial input shift register; in I2C mode it is four-state address input 0. |
| 8 | SDIN/SDA | bidirectional | In SPI mode this is the serial data input clocked on each falling edge of SCLK; in I2C mode it is the bidirectional SDA data line that requires an external pullup resistor to the supply voltage. |
| 9 | NC | unconnected | No connection; leave floating. |
| 10 | VREFIO | bidirectional | Reference output voltage pin when using the internal reference (default), or reference input when operating with an external reference. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD to AGND | -0.3 | 6 | V | 4 | |||
| Digital inputs to AGND | -0.3 | V | max VDD + 0.3 V | 4 | |||
| Output voltage VOUT to AGND | VOUT | -0.3 | V | max VDD + 0.3 V | 4 | ||
| VREFIO to AGND | VREFIO | -0.3 | V | max VDD + 0.3 V | 4 | ||
| Current into any digital pins | -10 | 10 | mA | 4 | |||
| Current into VDD, AGND, VOUT | -30 | 30 | mA | 4 | |||
| Current into VREFIO | -100 | 100 | mA | 4 | |||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Positive supply voltage to ground | VDD | 2.7 | 5.5 | V | VDD to AGND | 4 | |
| Input high voltage | VIH | 1.62 | V | 4 | |||
| Input low voltage | VIL | 0.45 | V | 4 | |||
| Reference input voltage | VREFIO | 1.2 | V | VREFIO to AGND, 2.7 V ≤ VDD < 3.3 V, reference divider disabled (REF-DIV bit = 0); max 0.5 × (VDD, 0.2) V | 4 | ||
| Reference input voltage | VREFIO | 2.4 | V | VREFIO to AGND, 2.7 V ≤ VDD < 3.3 V, reference divider enabled (REF-DIV bit = 1); max (VDD, 0.2) V | 4 | ||
| Operating temperature | TA | -40 | 125 | °C | 4 | ||
| Integral nonlinearity | INL | -1 | 1 | LSB | 5 | ||
| Differential nonlinearity | DNL | -1 | 1 | LSB | 5 | ||
| Total unadjusted error DAC80501 | TUE | -0.08 | -0.02 | 0.08 | %FSR | DAC80501, reference divider disabled (REF-DIV bit = 0) | 5 |
| Total unadjusted error DAC80501 | TUE | -0.06 | 0.025 | 0.06 | %FSR | DAC80501, reference divider enabled (REF-DIV bit = 1) | 5 |
| Total unadjusted error DAC80501 DGS package | TUE | -0.07 | 0.025 | 0.07 | %FSR | DAC80501, DGS package, reference divider enabled (REF-DIV bit = 1) | 5 |
| Zero code error | -1.5 | 0.5 | 1.5 | mV | DAC loaded with zero scale code | 5 | |
| Zero code error temperature coefficient | -2 | 2 | µV/°C | 5 | |||
| Offset error | -1.5 | 0.5 | 1.5 | mV | 5 | ||
| Offset error temperature coefficient | -2 | 2 | µV/°C | 5 | |||
| Gain error DAC80501 | -0.08 | -0.02 | 0.08 | %FSR | DAC80501, reference divider disabled (REF-DIV bit = 0) | 5 | |
| Gain error DAC80501 | -0.06 | 0.025 | 0.06 | %FSR | DAC80501, reference divider enabled (REF-DIV bit = 1) | 5 | |
| Gain error DAC80501 DGS package | -0.07 | 0.025 | 0.07 | %FSR | DAC80501, DGS package, reference divider enabled (REF-DIV bit = 1) | 5 | |
| Gain error temperature coefficient | -1 | 1 | ppm FSR/°C | 5 | |||
| Full-scale error DAC80501 | -0.08 | -0.02 | 0.08 | %FSR | DAC80501, DAC loaded with full scale, reference divider disabled (REF-DIV bit = 0) | 6 | |
| Full-scale error DAC80501 | -0.06 | 0.025 | 0.06 | %FSR | DAC80501, DAC loaded with full scale, reference divider enabled (REF-DIV bit = 1) | 6 | |
| Full-scale error DAC80501 DGS package | -0.07 | 0.025 | 0.07 | %FSR | DAC80501, DGS package, reference divider enabled (REF-DIV bit = 1) | 6 | |
| Full-scale error temperature coefficient | -2 | 2 | ppm FSR/°C | 6 | |||
| Output voltage | VO | 0 | V | BUFF-GAIN bit set to 1, REF-DIV bit set to 0; max 2 × VREFIO | 6 | ||
| Resistive load | RLOAD | 0.25 | kΩ | VDD = 2.7 V | 6 | ||
| Resistive load | RLOAD | 0.5 | kΩ | VDD = 5.5 V | 6 | ||
| Capacitive load | CLOAD | 2 | nF | RLOAD = infinite | 6 | ||
| Capacitive load | CLOAD | 10 | nF | RLOAD = 2 kΩ | 6 | ||
| Input current | -5 | 5 | µA | 8 | |||
| Current flowing into VDD, normal mode internal reference | IVDD | 1.5 | 2 | mA | Normal mode, internal reference enabled, DAC at full scale, SPI static | 8 | |
| Current flowing into VDD, normal mode external reference | IVDD | 1 | 1.4 | mA | Normal mode, external reference = 2.5 V, DAC at full scale, SPI static | 8 | |
| Junction-to-ambient thermal resistance | RθJA | 170.1 | °C/W | DGS (VSSOP) 10 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 60.5 | °C/W | DGS (VSSOP) 10 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 92.6 | °C/W | DGS (VSSOP) 10 pins | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 7.8 | °C/W | DGS (VSSOP) 10 pins | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 90.7 | °C/W | DGS (VSSOP) 10 pins | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | Use a hold capacitor that has high insulation resistance, low temperature coefficient, and low dielectric absorption. Low temperature coefficient NP0/C0G ceramic capacitors are a great choice for this | 35 |
CAD (KiCad official)
- Symbol:
DAC80501ZDGST - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
dac80501zdgst-etched.step/dac80501zdgst-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac80501zdgst.step/dac80501zdgst.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
51dcb60423765d25, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).