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Initial commit: component/dac80004ipwr

Ray ·eff2b4a6ce ·
2 files changed +228
README.mdadded+51
@@ -0,0 +1,51 @@+# DAC80004IPWR++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-14++DAC80004IPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LDAC | input | Load DAC register input, active low |+| 2 | SYNC | input | Serial interface synchronization input, active low |+| 3 | VDD | power_in | Positive power supply, 2.7 V to 5.5 V |+| 4 | VOUTA | output | DAC channel A analog output, 0 to REFIN volts |+| 5 | VOUTC | output | DAC channel C analog output, 0 to REFIN volts |+| 6 | POR | input | Power-on-reset control pin; GND selects zero scale, VDD selects midscale on power-up |+| 7 | REFIN | input | Reference voltage input for all DAC channels |+| 8 | SDO | output | Serial data output for readback and daisy-chain operations |+| 9 | CLR | input | Clear DAC register input, active on falling edge |+| 10 | VOUTD | output | DAC channel D analog output, 0 to REFIN volts |+| 11 | VOUTB | output | DAC channel B analog output, 0 to REFIN volts |+| 12 | GND | power_in | Ground return |+| 13 | SDIN | input | Serial data input |+| 14 | SCLK | input | Serial clock input, up to 50 MHz |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `DAC80004IPWR`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `dac80004ipwr-etched.step` / `dac80004ipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac80004ipwr.step` / `dac80004ipwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac70004) (44 pp, sha256 `17e505dbbc67542a`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac80004ipwr-datasheet.pdf)
page.jsonadded+177
@@ -0,0 +1,177 @@+{+  "slug": "dac80004ipwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "dac80004ipwr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "dac80004ipwr.kicad_sym",+    "dac80004ipwr.kicad_mod",+    "dac80004ipwr.glb",+    "dac80004ipwr.step",+    "dac80004ipwr.lbr",+    "docs/hero.png",+    "docs/dac80004ipwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "DAC80004IPWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-14",+    "pin_count": 14,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/dac70004",+    "parts": {+      "symbol": "dac80004ipwr.kicad_sym",+      "footprint": "dac80004ipwr.kicad_mod",+      "model_3d": "dac80004ipwr-etched.glb",+      "model_3d_plain": "dac80004ipwr.glb",+      "model_3d_step": "dac80004ipwr-etched.step",+      "model_3d_step_plain": "dac80004ipwr.step",+      "lbr": "dac80004ipwr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2679895"+    },+    "pins": [+      {+        "number": "1",+        "name": "LDAC",+        "type": "input",+        "description": "Load DAC register input, active low"+      },+      {+        "number": "2",+        "name": "SYNC",+        "type": "input",+        "description": "Serial interface synchronization input, active low"+      },+      {+        "number": "3",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive power supply, 2.7 V to 5.5 V"+      },+      {+        "number": "4",+        "name": "VOUTA",+        "type": "output",+        "description": "DAC channel A analog output, 0 to REFIN volts"+      },+      {+        "number": "5",+        "name": "VOUTC",+        "type": "output",+        "description": "DAC channel C analog output, 0 to REFIN volts"+      },+      {+        "number": "6",+        "name": "POR",+        "type": "input",+        "description": "Power-on-reset control pin; GND selects zero scale, VDD selects midscale on power-up"+      },+      {+        "number": "7",+        "name": "REFIN",+        "type": "input",+        "description": "Reference voltage input for all DAC channels"+      },+      {+        "number": "8",+        "name": "SDO",+        "type": "output",+        "description": "Serial data output for readback and daisy-chain operations"+      },+      {+        "number": "9",+        "name": "CLR",+        "type": "input",+        "description": "Clear DAC register input, active on falling edge"+      },+      {+        "number": "10",+        "name": "VOUTD",+        "type": "output",+        "description": "DAC channel D analog output, 0 to REFIN volts"+      },+      {+        "number": "11",+        "name": "VOUTB",+        "type": "output",+        "description": "DAC channel B analog output, 0 to REFIN volts"+      },+      {+        "number": "12",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return"+      },+      {+        "number": "13",+        "name": "SDIN",+        "type": "input",+        "description": "Serial data input"+      },+      {+        "number": "14",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock input, up to 50 MHz"+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 44,+        "cost_usd": 0.4302,+        "at": "2026-09-23T10:33:46"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/dac70004",+        "pages": 44,+        "sha256": "17e505dbbc67542a",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file