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DAC7822IRTAT

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Texas Instruments Digital To Analog Converters (DACs), WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersdac7822irtatfactory-2.0.0extractor-text

Verified DAC7822IRTAT

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC7822IRTAT · WQFN-40-EP(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C2679564, digikey 296-20636-2-ND, mouser 595-DAC7822IRTAT
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zj3w0q3l/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.22)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 52 kB, viewers/symbol.html 28 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac7822irtat.kicad_sym✓ dac7822irtat.kicad_mod✓ dac7822irtat.step
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DAC7822IRTAT

Texas Instruments · Digital To Analog Converters (DACs) · WQFN-40-EP(6x6)

DAC7822IRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R1A passive DAC A 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
2 R2A passive DAC A 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
3 R2_3A passive DAC A 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
4 R3A passive DAC A 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
5 VREFA input DAC A reference voltage input terminal for the multiplying R-2R DAC.
6 DGND power_in Digital ground pin.
7 LDAC input Load DAC input: when driven low the DAC updates asynchronously, and when held permanently low an automatic synchronous update occurs on the rising edge of CS.
8 DAC A/B input Selects DAC A when low and DAC B when high.
9 NC unconnected Not internally connected.
10 DB11 bidirectional Parallel data bit 11 (MSB) used to load data to the input latch or read back the DAC register.
11 DB10 bidirectional Parallel data bit 10 used to load data to the input latch or read back the DAC register.
12 DB9 bidirectional Parallel data bit 9 used to load data to the input latch or read back the DAC register.
13 DB8 bidirectional Parallel data bit 8 used to load data to the input latch or read back the DAC register.
14 DB7 bidirectional Parallel data bit 7 used to load data to the input latch or read back the DAC register.
15 DB6 bidirectional Parallel data bit 6 used to load data to the input latch or read back the DAC register.
16 DB5 bidirectional Parallel data bit 5 used to load data to the input latch or read back the DAC register.
17 DB4 bidirectional Parallel data bit 4 used to load data to the input latch or read back the DAC register.
18 DB3 bidirectional Parallel data bit 3 used to load data to the input latch or read back the DAC register.
19 DB2 bidirectional Parallel data bit 2 used to load data to the input latch or read back the DAC register.
20 DB1 bidirectional Parallel data bit 1 used to load data to the input latch or read back the DAC register.
21 DB0 bidirectional Parallel data bit 0 (LSB) used to load data to the input latch or read back the DAC register.
22 CS input Active-low chip select that is edge sensitive, with the DAC data latched when it is pulled high.
23 R/W input Read/write control: when low, used with CS to load parallel data; when high, used with CS to read back the DAC register contents.
24 CLR input Active-low control input that clears the DAC output, input and DAC registers.
25 VDD power_in Positive power supply input that can be operated from 2.5 V to 5.5 V.
26 VREFB input DAC B reference voltage input terminal for the multiplying R-2R DAC.
27 R3B passive DAC B 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
28 R2_3B passive DAC B 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
29 R2B passive DAC B 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
30 R1B passive DAC B 4-quadrant resistor that allows bipolar operation and other configuration modes with a minimum of external components.
31 RFBB output DAC B feedback resistor terminal connected to the external amplifier output.
32 IOUT2B power_in Analog ground for the DAC that typically ties to the system analog ground but can be biased to achieve single-supply operation.
33 IOUT1B output DAC B current output.
34 NC unconnected Not internally connected.
35 NC unconnected Not internally connected.
36 NC unconnected Not internally connected.
37 NC unconnected Not internally connected.
38 IOUT1A output DAC A current output.
39 IOUT2A power_in Analog ground for the DAC that typically ties to the system analog ground but can be biased to achieve single-supply operation.
40 RFBA output DAC A feedback resistor terminal connected to the external amplifier output.
41 EP passive Exposed thermal pad that must be soldered to the printed circuit board for optimal thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Data Converters
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD to GND VDD -0.3 7 V 2
Digital input voltage to GND -0.3 V Maximum printed as VDD + 0.3 V 2
VOUT to GND VOUT -0.3 V Maximum printed as VDD + 0.3 V 2
Operating temperature range -40 125 °C 2
Storage temperature range -65 150 °C 2
Junction temperature (TJ max) TJ 150 °C 2
ESD Rating, HBM 2000 V HBM 2
ESD Rating, CDM 1000 V CDM 2
Relative accuracy -1 1 LSB 3
Differential nonlinearity DNL -1 1 LSB 3
Output leakage current -1 1 nA Data = 000h, TA = +25°C 3
Output leakage current -15 15 nA Data = 000h, TA = TMAX 3
Full-scale gain error -25 10 25 mV All ones loaded to DAC register 3
Full-scale tempco -5 5 ppm/°C 3
Bipolar zero-code error -25 25 mV Circuit configuration as shown in Figure 41 3
Output capacitance 25 30 pF DAC latches leaded with all 1s 3
VREF range VREF -15 15 V 3
VREFA, VREFB input resistance 8 10 12 kΩ 3
R1, RFB resistance 17 20 25 kΩ 3
R2, R3 resistance 17 20 25 kΩ 3
VREFA to VREFB input mismatch 1.6 2.5 % 3
R2 to R3 mismatch 0.06 0.18 % 3
Input low voltage VIL 0.6 V VDD = +2.5V 3
Input low voltage VIL 0.8 V VDD = +5V 3
Input high voltage VIH 2.1 V VDD = +2.5V 3
Input high voltage VIH 2.4 V VDD = +5V 3
Input leakage current IIL 1 µA 3
Supply voltage VDD 2.5 5.5 V 3
IDD (normal operation) IDD 5 µA Logic inputs = 0V 3
IDD IDD 0.8 5 µA VDD = +4.5V to +5.5V, VIH = VDD and VIL = GND 3
IDD IDD 0.4 2.5 µA VDD = +2.5V to +3.6V, VIH = VDD and VIL = GND 3
R/W to CS setup time t1 0 ns 4
R/W to CS hold time t2 0 ns 4
CS low time (write cycle) t3 10 ns 4
Address setup time t4 10 ns 4
Address hold time t5 0 ns 4
Data setup time t6 6 ns 4
Data hold time t7 0 ns 4
R/W high to CS low t8 5 ns 4
CS minimum high time t9 7 ns 4
Address setup time (Read Cycle) t10 0 ns 4
Address hold time (Read Cycle) t11 0 ns 4
Data access time t12 5 35 ns 4
Bus relinquish time t13 5 10 ns 4
R-2R ladder load impedance tolerance (VREF input) -20 20 % Nominal 10 kΩ, code-independent 13

CAD (KiCad official)

  • Symbol: DAC7822IRTAT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm tall, datasheet A, max). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: dac7822irtat-etched.step / dac7822irtat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7822irtat.step / dac7822irtat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 a8f8e4be8cb38074, retrieved 2026-11-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF