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DAC7811IDGSTG4

Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm

DAC7811IDGSTG4 from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOUT1 output DAC current output (IOUT1) of the 12-bit R-2R DAC.
2 IOUT2 output DAC current output (IOUT2) per the pin name; the pin table row carries analog-ground wording that conflicts with this and must be verified.
3 GND power_in Ground pin.
4 SCLK input Serial clock input; by default data is clocked into the input shift register on the falling edge, and the device can be configured for the rising edge via serial control bits.
5 SDIN input Serial data input clocked into the 16-bit input register on the active edge of SCLK, with falling edge as the power-on default.
6 SYNC input Active-low frame synchronization input; when SYNC goes low it powers on the SCLK and DIN buffers and enables the input shift register.
7 SDO output Serial data output that allows daisy-chaining of parts and provides DAC register readback on the opposite clock edge.
8 VDD power_in Positive power supply input; the parts can be operated from a supply of 2.7 V to 5.5 V.
9 VREF power_in DAC reference voltage input; the recommended reference voltage range is -15 V to 15 V.
10 RFB output DAC feedback resistor pin; establishes the DAC voltage output when connected to an external amplifier output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-10-0.5mm
Category Data Acquisition
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage to GND VDD 2.7 5.5 V 4
Reference voltage VREF -15 15 V 4
Input low voltage VIL 0.6 V VDD = 2.7 V 4
Input low voltage VIL 0.8 V VDD = 5 V 4
Input high voltage VIH 2.1 V VDD = 2.7 V 4
Input high voltage VIH 2.4 V VDD = 5 V 4
Operating ambient temperature TA -40 125 °C 4
VDD to GND VDD -0.3 7 V 4
Digital input voltage to GND -0.3 V 4
IOUT1, IOUT2 to GND IOUT1, IOUT2 -0.3 V 4
Operating temperature -40 125 °C 4
Junction temperature (TJ max) TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Electrostatic discharge, Human-body model (HBM) V(ESD) -2000 2000 V per ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, Charged-device model (CDM) V(ESD) -1000 1000 V per JEDEC JESD22-C101 4
Relative accuracy -1 1 LSB 5
Differential nonlinearity -1 1 LSB 5
Output leakage current -5 5 nA Data = 0000h, TA = 25°C 5
Output leakage current -25 25 nA Data = 0000h, TA = TMAX 5
Full-scale gain error 5 10 mV All ones loaded to DAC register 5
Full-scale tempco -5 5 ppm/°C 5
Input resistance 8 10 12 kΩ 5
RFB resistance RFB 8 10 12 kΩ 5
Input leakage current IIL 10 µA 5
Reference multiplying BW 10 MHz VREF = 7 VPP, Data = FFFh 5
Clock frequency fCLK 50 MHz 5
Clock period tC 20 ns 5
Clock pulse width high tCH 8 ns 5
Clock pulse width low tCC 8 ns 5
SYNC falling edge to SCLK active edge setup time tCSS 13 ns 5
SCLK active edge to SYNC rising edge hold time tCST 5 ns 5
Data setup time tDS 5 ns 5
Data hold time tDH 3 ns 5
SYNC high time tSH 30 ns 5
SYNC inactive edge to SDO valid tDDS 25 35 ns VDD = 2.7 V 5
SYNC inactive edge to SDO valid tDDS 20 30 ns VDD = 5 V 5
IDD (normal operation) IDD 5 µA Logic inputs = 0 V 5
IDD (normal operation) IDD 0.8 5 µA VDD = 4.5 V to 5.5 V, VIH = VDD and VIL = GND 5
IDD (normal operation) IDD 0.4 2.5 µA VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND 5
Output capacitance 5 pF Code dependent 5
Input capacitance CIL 10 pF 5
Output voltage settling time 0.2 µs 5
DAC glitch impulse 5 nV-s VREF = 0 V to 10 V, Data = 7FFh to 800h to 7FFh 5
Feedthrough error VOUT/VREF -60 dB Data = 000h, VREF = 100 kHz 5
Digital feedthrough 2 nV-s 5
Total harmonic distortion THD -105 dB 5
Output spot noise voltage 18 nV/√Hz 5
Junction-to-ambient thermal resistance RθJA 165.6 °C/W DGS (VSSOP) 10 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 55.4 °C/W DGS (VSSOP) 10 pins 4
Junction-to-board thermal resistance RθJB 85.6 °C/W DGS (VSSOP) 10 pins 4
Junction-to-top characterization parameter ψJT 6.2 °C/W DGS (VSSOP) 10 pins 4
Junction-to-board characterization parameter ψJB 84.2 °C/W DGS (VSSOP) 10 pins 4

CAD (KiCad official)

  • Symbol: DAC7811IDGSTG4
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
  • 3D model files: dac7811idgstg4-etched.step / dac7811idgstg4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7811idgstg4.step / dac7811idgstg4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 b8c9f325a70219e2, retrieved 2026-11-06, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF