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DAC7731EC

Texas Instruments · Digital To Analog Converters (DACs) · SSOP-24

DAC7731EC from Texas Instruments, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Positive analog power supply; the electrical characteristics specify +11.4V to +15.75V.
2 REFOUT output Internal +10V reference output, enabled when REFEN is LOW and connected to REFIN for internal reference use.
3 REFIN input Reference input to the on-chip buffer, which must be between 4.75V (or VSS + 14V, whichever is greater) and VCC - 1.4V when an external reference is used.
4 REFADJ input Internal reference trim pin that acts as a gain adjustment input when the internal reference is used.
5 VREF power_in Buffered output from REFIN that drives the DAC circuitry internally and may drive external devices, rated at -2 mA to +2 mA.
6 ROFFSET passive Offsetting resistor connection in the output range configuration network.
7 AGND power_in Analog ground return, to be kept separate from DGND and joined at the system power-entry point.
8 RFB2 passive Feedback resistor 2, used to configure the DAC output range.
9 RFB1 passive Feedback resistor 1, used to configure the DAC output range.
10 SJ input Summing junction of the output amplifier.
11 VOUT output DAC voltage output, configurable for 0V to +10V, ±5V, or ±10V ranges, with a maximum load capacitance of 200pF.
12 VDD power_in Digital power supply, specified from +4.75V to +5.25V (+5.0V typical).
13 DGND power_in Digital ground return for the logic and serial interface, kept separate from AGND.
14 TEST passive Reserved pin that must be connected to DGND.
15 NC unconnected No connection.
16 RST input Active-LOW asynchronous reset that sets the DAC register to mid-scale or min-scale depending on RSTSEL; Schmitt-triggered input.
17 LDAC input DAC register load control, rising-edge triggered, that transfers data from the input register to the DAC register; Schmitt-triggered input.
18 SDI input Serial data input, latched into the input register on the rising edge of SCLK; Schmitt-triggered input.
19 SDO tri_state Serial data output, delayed by 16 SCLK cycles, enabled from high impedance when CS is LOW.
20 CS input Active-LOW chip select that enables the serial shift operation; a rising CS edge should occur only when SCLK is HIGH.
21 SCLK input Serial clock input that clocks data into the input register; Schmitt-triggered input.
22 RSTSEL input Reset select that sets the action of RST: HIGH resets the DAC register to mid-scale, LOW resets it to min-scale.
23 REFEN input Active-LOW enable for the internal +10V reference; HIGH disables the reference and places REFOUT in high impedance.
24 VSS power_in Negative analog power supply, -11.4V to -15.75V for bipolar operation and -4.75V to -15.75V for unipolar operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-24
Category ADC/DAC/Data Conversion
Pins 24

CAD (KiCad official)

  • Symbol: DAC7731EC
  • Footprint: Package_SO:SSOP-24_5.3x8.2mm_P0.65mm
  • 3D model: SSOP-24 (KiCad packages3D, STEP)
  • 3D model files: dac7731ec-etched.step / dac7731ec-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7731ec.step / dac7731ec.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 031c070247652ea7, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF