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DAC7573IPW

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16

DAC7573IPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A, with an output voltage range of 0 to VREFH V.
2 VOUTB output Analog output voltage from DAC B, with an output voltage range of 0 to VREFH V.
3 VREFH input Positive reference voltage input, with an input range of 0 to VDD V.
4 VDD power_in Analog voltage supply input, specified from +2.7 V to +5.5 V.
5 VREFL input Negative reference voltage input, with an input range of 0 to VDD V and VREFL < VREFH required.
6 GND power_in Ground reference point for all circuitry on the part.
7 VOUTC output Analog output voltage from DAC C, with an output voltage range of 0 to VREFH V.
8 VOUTD output Analog output voltage from DAC D, with an output voltage range of 0 to VREFH V.
9 LDAC input Hardware synchronous VOUT update input that transfers the buffered DAC data to the outputs.
10 SCL input Serial clock input for the I2C interface, supporting up to 3.4 Mbps.
11 SDA bidirectional Serial data line for the I2C interface.
12 IOVDD power_in I/O voltage supply input for the digital interface, with logic thresholds of 0.3xIOVDD (low) and 0.7xIOVDD (high).
13 A0 input Device address select for the I2C interface.
14 A1 input Device address select for the I2C interface.
15 A2 input Device address select for extended addressing.
16 A3 input Device address select for extended addressing.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Acquisition
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative accuracy -8 8 LSB 3
Differential nonlinearity -1 1 LSB Specified monotonic by design 3
Zero-scale error 5 20 mV 3
Full-scale error -1 -0.15 1 % of FSR 3
Gain error -1 1 % of FSR 3
Zero code error drift -7 7 µV/°C 3
Gain temperature coefficient -3 3 ppm of FSR/°C 3
Output voltage range VOUT 0 V Maximum is VREFH 3
Output voltage settling time (full scale) 8 10 µs RL = ∞; 0 pF < CL < 200 pF 3
Output voltage settling time (full scale) 12 µs RL = ∞; CL = 500 pF 3
Slew rate 1 V/µs 3
DC crosstalk (channel-to-channel) 0.02 LSB 3
AC crosstalk (channel-to-channel) -100 dB 1 kHz Sine Wave 3
Capacitive load stability 470 pF RL= ∞ 3
Capacitive load stability 1000 pF RL= 2 kΩ 3
Digital-to-analog glitch impulse 12 nV-s 1 LSB change around major carry 3
Digital feedthrough 0.3 nV-s 3
DC output impedance 1 Ω 3
Short-circuit current 50 mA VDD= 5 V 3
Short-circuit current 20 mA VDD= 3 V 3
Power-up time 2.5 µs Coming out of power-down mode, VDD= +5 V 3
Power-up time 5 µs Coming out of power-down mode, VDD= +3 V 3
VREFH input range VREFH 0 V Maximum is VDD 3
VREFL input range VREFL 0 V VREFL<VREFH; maximum is VDD 3
Reference input impedance 25 kΩ 3
Reference current 185 260 µA VREF=VDD = +5 V 3
Reference current 122 200 µA VREF=VDD = +3 V 3
Input current -1 1 µA 3
Input low voltage VIN_L 0.3 V Value is 0.3xIOVDD 3
Input high voltage VIN_H 0.7 V VDD= 3 V; value is 0.7xIOVDD 3
Pin capacitance 3 pF 3
Supply voltage VDD, IOVDD VDD, IOVDD 2.7 5.5 V 3
Supply current normal operation IDD 600 900 µA VDD=+3.6V to +5.5V; VIH= IOVDD and VIL=GND; excluding load current 3
Supply current normal operation IDD 550 750 µA VDD =+2.7V to +3.6V; VIH= IOVDD and VIL=GND; excluding load current 3
Supply current power-down IDD 0.2 1 µA VDD=+3.6V to +5.5V; VIH= IOVDD and VIL=GND 4
Supply current power-down IDD 0.05 1 µA VDD =+2.7V to +3.6V; VIH= IOVDD and VIL=GND 4
Power efficiency IOUT/IDD 93 % ILOAD= 2 mA, VDD= +5 V 4
Specified performance temperature range -40 105 °C 4
SCL clock frequency standard mode fSCL 100 kHz Standard mode 4
SCL clock frequency fast mode fSCL 400 kHz Fast mode 4
SCL clock frequency high-speed mode fSCL 3.4 MHz High-Speed mode, CB = 100 pF max 4
SCL clock frequency high-speed mode fSCL 1.7 MHz High-speed mode, CB = 400 pF max 4
Absolute max VDD to GND VDD -0.3 6 V 2
Absolute max VOUT to GND VOUT -0.3 V Maximum is VDD + 0.3 V 2
Absolute max digital input voltage to GND -0.3 V Maximum is VDD + 0.3 V 2
Operating temperature range -40 105 °C 2
Storage temperature range -65 150 °C 2
Junction temperature range (TJ max) TJ 150 °C 2
Lead temperature vapor phase (60 s) 215 °C Vapor phase (60s) 2
Lead temperature infrared (15 s) 220 °C Infrared (15s) 2
Thermal impedance junction-to-ambient ΘJA 161 °C/W 2
Thermal impedance junction-to-case ΘJC 29 °C/W 2

CAD (KiCad official)

  • Symbol: DAC7573IPW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: dac7573ipw-etched.step / dac7573ipw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7573ipw.step / dac7573ipw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 3a0ce5356d0f5505, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF