component
DAC7565IAPWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownDAC7565IAPWR
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC7565IAPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A (0V to VREF range, ±20mA sink/source capability). |
| 2 | VOUTB | output | Analog output voltage from DAC B (0V to VREF range, ±20mA sink/source capability). |
| 3 | VREFH/VREFOUT | bidirectional | Positive reference input or 2.5V internal reference output (enabled by default) with ±20mA load current capability. |
| 4 | AVDD | power_in | Analog power supply input (2.7V to 5.5V). |
| 5 | VREFL | input | Negative reference input (0V to AVDD/2 operating range). |
| 6 | GND | power_in | Ground reference point for all circuitry. |
| 7 | VOUTC | output | Analog output voltage from DAC C (0V to VREF range, ±20mA sink/source capability). |
| 8 | VOUTD | output | Analog output voltage from DAC D (0V to VREF range, ±20mA sink/source capability). |
| 9 | SYNC | input | Active-low frame synchronization input enabling 24-bit data shift with rising edge interrupt capability. |
| 10 | SCLK | input | Serial clock input accepting data at rates up to 50MHz with Schmitt-trigger logic. |
| 11 | DIN | input | Serial data input accepting MSB-first data on each SCLK falling edge with Schmitt-trigger logic. |
| 12 | IOVDD | power_in | Digital power supply input (1.8V to 5.5V, typically 2.7V to 5.5V). |
| 13 | RST | input | Active-low asynchronous reset input resetting all channels to zero-scale or mid-scale as selected by RSTSEL. |
| 14 | RSTSEL | input | Reset select and input coding format control (low = zero-scale/binary mode, high = mid-scale/two's complement mode). |
| 15 | ENABLE | input | Active-low enable input connecting/disconnecting the SPI serial interface. |
| 16 | LDAC | input | Rising-edge triggered load input simultaneously updating all DAC outputs from their buffers. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC7565IAPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac7565iapwr-etched.step/dac7565iapwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac7565iapwr.step/dac7565iapwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
676bd6014edb5cf1, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).