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Initial commit: component/dac7562sdgsr

Ray ·177d7aef1e ·3d ago
2 files changed +215
README.mdadded+46
@@ -0,0 +1,46 @@+# DAC7562SDGSR++**Texas Instruments** · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm++DAC7562SDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUTA | output | Analog output voltage from DAC-A providing the converted digital-to-analog output for channel A. |+| 2 | VOUTB | output | Analog output voltage from DAC-B providing the converted digital-to-analog output for channel B. |+| 3 | GND | power_in | Ground reference point for all circuitry on the device. |+| 4 | LDAC | input | Negative-edge-triggered latch signal for simultaneous DAC updates; in synchronous mode must be connected to GND, in asynchronous mode enables multiple single-channel writes with simultaneous update on LDAC falling edge. |+| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads zero scale or mid-scale to all input and DAC registers and exits clear mode on the 24th falling edge of the next write sequence. |+| 6 | SYNC | input | Level-triggered control input (active-low) serving as frame synchronization signal that enables the input shift register and triggers DAC update on the 24th falling clock edge with Schmitt-trigger logic. |+| 7 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic. |+| 8 | DIN | input | Serial data input clocking 24-bit words into the input shift register on each falling clock edge with Schmitt-trigger logic. |+| 9 | AVDD | power_in | Power-supply input accepting 2.7 V to 5.5 V for device operation. |+| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin outputting 2.5 V when internal reference is enabled or accepting external reference input from 0 V to AVDD, with ±5 mV initial accuracy and 20 mA source/sink capability. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-10-0.5mm |+| Category | Data Acquisition |+| Pins | 10 |++## CAD (KiCad official)++- Symbol: `DAC7562SDGSR`+- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`+- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)+- 3D model files: `dac7562sdgsr-etched.step` / `dac7562sdgsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac7562sdgsr.step` / `dac7562sdgsr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac8563) (63 pp, sha256 `3fbba20baac4cf7e`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac7562sdgsr-datasheet.pdf)
page.jsonadded+169
@@ -0,0 +1,169 @@+{+  "slug": "dac7562sdgsr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital To Analog Converters (DAC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "dac7562sdgsr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "dac7562sdgsr.kicad_sym",+    "dac7562sdgsr.kicad_mod",+    "dac7562sdgsr.glb",+    "dac7562sdgsr.step",+    "dac7562sdgsr.lbr",+    "docs/hero.png",+    "docs/dac7562sdgsr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "dac7562sdgsr-hero.glb",+    "dac7562sdgsr-hero.overlay.json"+  ],+  "component": {+    "mpn": "DAC7562SDGSR",+    "manufacturer": "Texas Instruments",+    "package": "VSSOP-10-0.5mm",+    "pin_count": 10,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/dac8563",+    "parts": {+      "symbol": "dac7562sdgsr.kicad_sym",+      "footprint": "dac7562sdgsr.kicad_mod",+      "model_3d": "dac7562sdgsr-hero.glb",+      "model_3d_plain": "dac7562sdgsr.glb",+      "model_3d_step": "dac7562sdgsr-etched.step",+      "model_3d_step_plain": "dac7562sdgsr.step",+      "lbr": "dac7562sdgsr.lbr"+    },+    "distributor_links": {+      "lcsc": 1554786,+      "digikey": "296-29022-2-ND",+      "mouser": "595-DAC7562SDGSR"+    },+    "distributor_check": {+      "checked_at": "2026-10-03T03:53:18Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-29022-2-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-DAC7562SDGSR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "VOUTA",+        "type": "output",+        "description": "Analog output voltage from DAC-A providing the converted digital-to-analog output for channel A."+      },+      {+        "number": "2",+        "name": "VOUTB",+        "type": "output",+        "description": "Analog output voltage from DAC-B providing the converted digital-to-analog output for channel B."+      },+      {+        "number": "3",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference point for all circuitry on the device."+      },+      {+        "number": "4",+        "name": "LDAC",+        "type": "input",+        "description": "Negative-edge-triggered latch signal for simultaneous DAC updates; in synchronous mode must be connected to GND, in asynchronous mode enables multiple single-channel writes with simultaneous update on LDAC falling edge."+      },+      {+        "number": "5",+        "name": "CLR",+        "type": "input",+        "description": "Falling-edge-sensitive asynchronous clear input that loads zero scale or mid-scale to all input and DAC registers and exits clear mode on the 24th falling edge of the next write sequence."+      },+      {+        "number": "6",+        "name": "SYNC",+        "type": "input",+        "description": "Level-triggered control input (active-low) serving as frame synchronization signal that enables the input shift register and triggers DAC update on the 24th falling clock edge with Schmitt-trigger logic."+      },+      {+        "number": "7",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic."+      },+      {+        "number": "8",+        "name": "DIN",+        "type": "input",+        "description": "Serial data input clocking 24-bit words into the input shift register on each falling clock edge with Schmitt-trigger logic."+      },+      {+        "number": "9",+        "name": "AVDD",+        "type": "power_in",+        "description": "Power-supply input accepting 2.7 V to 5.5 V for device operation."+      },+      {+        "number": "10",+        "name": "VREFIN/VREFOUT",+        "type": "bidirectional",+        "description": "Bidirectional voltage reference pin outputting 2.5 V when internal reference is enabled or accepting external reference input from 0 V to AVDD, with ±5 mV initial accuracy and 20 mA source/sink capability."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 13,+        "cost_usd": 0.1183,+        "at": "2026-10-03T03:52:51"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/dac8563",+        "pages": 63,+        "sha256": "3fbba20baac4cf7e",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 10,+        "described": 10,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file