component
DAC7562SDGSR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownDAC7562SDGSR
Texas Instruments · Digital To Analog Converters (DAC) · VSSOP-10-0.5mm
DAC7562SDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC-A providing the converted digital-to-analog output for channel A. |
| 2 | VOUTB | output | Analog output voltage from DAC-B providing the converted digital-to-analog output for channel B. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | LDAC | input | Negative-edge-triggered latch signal for simultaneous DAC updates; in synchronous mode must be connected to GND, in asynchronous mode enables multiple single-channel writes with simultaneous update on LDAC falling edge. |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads zero scale or mid-scale to all input and DAC registers and exits clear mode on the 24th falling edge of the next write sequence. |
| 6 | SYNC | input | Level-triggered control input (active-low) serving as frame synchronization signal that enables the input shift register and triggers DAC update on the 24th falling clock edge with Schmitt-trigger logic. |
| 7 | SCLK | input | Serial clock input supporting data transfer rates up to 50 MHz with Schmitt-trigger logic. |
| 8 | DIN | input | Serial data input clocking 24-bit words into the input shift register on each falling clock edge with Schmitt-trigger logic. |
| 9 | AVDD | power_in | Power-supply input accepting 2.7 V to 5.5 V for device operation. |
| 10 | VREFIN/VREFOUT | bidirectional | Bidirectional voltage reference pin outputting 2.5 V when internal reference is enabled or accepting external reference input from 0 V to AVDD, with ±5 mV initial accuracy and 20 mA source/sink capability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
DAC7562SDGSR - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
dac7562sdgsr-etched.step/dac7562sdgsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac7562sdgsr.step/dac7562sdgsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
3fbba20baac4cf7e, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).