component

DAC7553IRGTR

Public Made by Adom

by adom

Texas Instruments Digital To Analog Converters (DACs), VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiondac7553irgtrfactory-2.0.0extractor-text

Verified DAC7553IRGTR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC7553IRGTR · VQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 26-page datasheet
  • ✓distributor: lcsc C2862726, digikey DAC7553IRGTR-ND, mouser 595-DAC7553IRGTR
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pld8qun9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.23)
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac7553irgtr.kicad_sym✓ dac7553irgtr.kicad_mod✓ dac7553irgtr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers dac7553irgtr: viewers · Ray 4d ago
dac7553irgtr-etched.glb Publish 0.1.0 · Ray 4d ago
dac7553irgtr-etched.step dac7553irgtr: factory component page (tier=mfr) · Ray 4d ago
dac7553irgtr-hero.glb dac7553irgtr: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
dac7553irgtr-hero.overlay.json Publish 0.1.0 · Ray 4d ago
dac7553irgtr.glb Publish 0.1.0 · Ray 4d ago
dac7553irgtr.kicad_mod Publish 0.1.0 · Ray 4d ago
dac7553irgtr.kicad_sym Publish 0.1.0 · Ray 4d ago
dac7553irgtr.lbr Publish 0.1.0 · Ray 4d ago
dac7553irgtr.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 4d ago

DAC7553IRGTR

Texas Instruments · Digital To Analog Converters (DACs) · VQFN-16-EP(3x3)

DAC7553IRGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A, rail-to-rail, range 0 to VREF.
2 VDD power_in Analog voltage supply input, 2.7 V to 5.5 V.
3 GND power_in Ground.
4 VOUTB output Analog output voltage from DAC B, rail-to-rail, range 0 to VREF.
5 VFBB input DAC B amplifier sense input.
6 VREFB input Positive reference voltage input for DAC B, range 0 to VDD.
7 PD input Power down input.
8 DCEN input Daisy-chain enable input.
9 SDO output Serial data output.
10 IOVDD power_in I/O voltage supply input for the digital interface.
11 SYNC input Frame synchronization input; the falling edge of the SYNC pulse indicates the start of a serial data frame shifted into the DAC7553.
12 SCLK input Serial clock input, up to 50 MHz.
13 SDIN input Serial data input.
14 CLR input Asynchronous input to clear the DAC registers; when low, the DAC registers are set to 000H and the output to midscale voltage.
15 VREFA input Positive reference voltage input for DAC A, range 0 to VDD.
16 VFBA input DAC A amplifier sense input.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative accuracy INL -1 0.35 1 LSB Linearity tested using reduced code range 30 to 4065; output unloaded 3
Differential nonlinearity DNL -0.5 0.08 0.5 LSB Specified monotonic by design 3
Offset error -12 12 mV 3
Zero-scale error -12 12 mV All zeroes loaded to DAC register 3
Gain error -0.15 0.15 %FSR 3
Full-scale error -0.5 0.5 %FSR 3
Output voltage settling time 5 µs RL = 2 kΩ; 0 pF < CL < 200 pF 3
Reference current 100 250 µA VREFA = VREFB = VDD = 5 V, VREFA and VREFB shorted together 3
Reference current 60 123 µA VREFA = VREFB = VDD = 3 V, VREFA and VREFB shorted together 3
Logic input current -1 1 µA 3
Input low voltage VIN_L 0.3 V IOVDD ≥ 2.7 V; max = 0.3 IOVDD 3
Input high voltage VIN_H 0.7 V IOVDD ≥ 2.7 V; min = 0.7 IOVDD 3
Supply voltage VDD, IOVDD 2.7 5.5 V 4
IDD normal operation IDD 300 440 µA VDD = 3.6 V to 5.5 V; VIH = IOVDD and VIL = GND 4
IDD normal operation IDD 250 400 µA VDD = 2.7 V to 3.6 V; VIH = IOVDD and VIL = GND 4
IDD all power-down modes IDD 0.2 2 µA VDD = 3.6 V to 5.5 V; VIH = IOVDD and VIL = GND 4
IDD all power-down modes IDD 0.05 2 µA VDD = 2.7 V to 3.6 V; VIH = IOVDD and VIL = GND 4
SCLK cycle time t1 20 ns VDD = 2.7 V to 5.5 V 5
SCLK HIGH time t2 10 ns VDD = 2.7 V to 5.5 V 5
SCLK LOW time t3 10 ns VDD = 2.7 V to 5.5 V 5
SYNC falling edge to SCLK falling edge setup time t4 4 ns VDD = 2.7 V to 5.5 V 5
Data setup time t5 5 ns VDD = 2.7 V to 5.5 V 5
Data hold time t6 4.5 ns VDD = 2.7 V to 5.5 V 5
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 5
Minimum SYNC HIGH time t8 20 ns VDD = 2.7 V to 5.5 V 5
SCLK falling edge to SDO valid t9 10 ns VDD = 2.7 V to 5.5 V 5
CLR pulse width low t10 10 ns VDD = 2.7 V to 5.5 V 5
VDD to GND VDD -0.3 6 V 2
Digital input voltage to GND -0.3 6 V -0.3 V to VDD + 0.3 V 2
Vout to GND VOUT -0.3 6 V -0.3 V to VDD + 0.3 V 2
Operating temperature range -40 105 °C 2
Storage temperature range -65 150 °C 2
Junction temperature TJ Max 150 °C 2
Resolution 12 Bits 3
Zero-scale error drift 7 µV/°C 3
Gain temperature coefficient 3 ppm of FSR/°C 3
PSRR PSRR 0.75 mV/V VDD = 5 V 3
Slew rate 1.8 V/µs 3
Output voltage range 0 V upper limit VREF 3
VREF input range VREF 0 V upper limit VDD 3
Reference input impedance 50 kΩ VREFA and VREFB shorted together 3
Short-circuit current 50 mA VDD = 5 V 3
Short-circuit current 20 mA VDD = 3 V 3
Power-up time 15 µs Coming out of power-down mode, VDD = 5 V 3
Digital-to-analog glitch impulse 0.1 nV-s 1 LSB change around major carry 3
Channel-to-channel crosstalk -100 dB 1-kHz full-scale sine wave, outputs unloaded 3
Output noise density 120 nV/rtHz 10-kHz offset frequency 3
Total harmonic distortion THD -85 dB FOUT = 1 kHz, FS = 1 MSPS, BW = 20 kHz 3

CAD (KiCad official)

  • Symbol: DAC7553IRGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: dac7553irgtr-etched.step / dac7553irgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac7553irgtr.step / dac7553irgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 2d8f67ce79fb077b, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF