# DAC70501MDGSR

**Texas Instruments** · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm

DAC70501MDGSR from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Analog supply voltage, specified from 2.7 V to 5.5 V. |
| 2 | VOUT | output | Analog output voltage from the DAC, with the full-scale range set by the internal reference to 1.25 V, 2.5 V, or 5 V. |
| 3 | NC | unconnected | No connection; leave floating. |
| 4 | AGND | power_in | Ground reference point for all circuitry on the device. |
| 5 | SPI2C | input | Interface select pin: SPI mode when low (SPI2C = 0), I2C mode when high (SPI2C = 1), and it must be kept static after power-up. |
| 6 | SCLK/SCL | input | Serial interface clock for SPI or I2C mode. |
| 7 | SYNC/A0 | input | In SPI mode, an active-low frame synchronization input that enables the serial input shift register; in I2C mode, four-state address input 0. |
| 8 | SDIN/SDA | bidirectional | In SPI mode, serial data input clocked on each falling edge of SCLK; in I2C mode, bidirectional SDA data line that must be pulled up to the supply through an external resistor. |
| 9 | NC | unconnected | No connection; leave floating. |
| 10 | VREFIO | bidirectional | Reference output voltage pin when using the internal 2.5 V reference (default), or reference input when operating with an external reference. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to AGND | VDD | -0.3 |  | 6 | V |  | 4 |
| VREFIO to AGND | VREFIO | -0.3 |  |  | V | max printed as VDD + 0.3 V | 4 |
| Digital inputs to AGND |  | -0.3 |  |  | V | max printed as VDD + 0.3 V | 4 |
| Output voltage VOUT to AGND | VOUT | -0.3 |  |  | V | max printed as VDD + 0.3 V | 4 |
| Current into any digital pins |  | -10 |  | 10 | mA |  | 4 |
| Current into VDD, AGND, VOUT |  | -30 |  | 30 | mA |  | 4 |
| Current into VREFIO |  | -100 |  | 100 | mA |  | 4 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Positive supply voltage (VDD to AGND) | VDD | 2.7 |  | 5.5 | V |  | 4 |
| Input high voltage | VIH | 1.62 |  |  | V |  | 4 |
| Input low voltage | VIL |  |  | 0.45 | V |  | 4 |
| VREFIO to AGND reference input | VREFIO | 1.2 |  |  | V | 2.7 V ≤ VDD < 3.3 V, reference divider disabled (REF-DIV bit = 0); max printed as 0.5 × (VDD, 0.2) | 4 |
| VREFIO to AGND reference input | VREFIO | 2.4 |  |  | V | 2.7 V ≤ VDD < 3.3 V, reference divider enabled (REF-DIV bit = 1); max printed as VDD, 0.2 | 4 |
| Operating temperature | TA | -40 |  | 125 | °C |  | 4 |
| Integral nonlinearity | INL | -1 |  | 1 | LSB |  | 5 |
| Differential nonlinearity | DNL | -1 |  | 1 | LSB |  | 5 |
| Total unadjusted error | TUE | -0.1 | 0.04 | 0.1 | %FSR | DAC70501, DAC60501 | 5 |
| Zero code error |  | -1.5 | 0.5 | 1.5 | mV | DAC loaded with zero scale code | 5 |
| Zero code error temperature coefficient |  | -2 |  | 2 | µV/°C |  | 5 |
| Offset error |  | -1.5 | 0.5 | 1.5 | mV |  | 5 |
| Offset error temperature coefficient |  | -2 |  | 2 | µV/°C |  | 5 |
| Gain error |  | -0.1 | 0.04 | 0.1 | %FSR | DAC70501, DAC60501 | 5 |
| Gain error temperature coefficient |  | -1 |  | 1 | ppm FSR/°C |  | 5 |
| Full-scale error |  | -0.1 | 0.04 | 0.1 | %FSR | DAC70501, DAC60501 | 6 |
| Full-scale error temperature coefficient |  | -2 |  | 2 | ppm FSR/°C |  | 6 |
| Output voltage | VO | 0 |  |  | V | BUFF-GAIN bit set to 1, REF-DIV bit set to 0; max printed as 2 × VREFIO | 6 |
| Resistive load | RLOAD | 0.25 |  |  | kΩ | VDD = 2.7 V | 6 |
| Resistive load | RLOAD | 0.5 |  |  | kΩ | VDD = 5.5 V | 6 |
| Capacitive load | CLOAD |  |  | 2 | nF | RLOAD = infinite | 6 |
| Capacitive load | CLOAD |  |  | 10 | nF | RLOAD = 2 kΩ | 6 |
| Initial accuracy of voltage reference output |  | 2.4975 |  | 2.5025 | V | TA = 25°C | 7 |
| Output drift of voltage reference |  |  |  | 10 | ppm/°C | DAC70501, DAC60501 | 7 |
| Load current of voltage reference |  | -5 |  | 5 | mA | -0.5 mV < ΔVref < 0.5 mV | 7 |
| Input current |  | -5 |  | 5 | µA |  | 8 |
| Current flowing into VDD, normal mode, internal reference enabled | IVDD |  | 1.5 | 2 | mA | Normal mode, internal reference enabled, DAC at full scale, SPI static | 8 |
| Current flowing into VDD, normal mode, external reference = 2.5 V | IVDD |  | 1 | 1.4 | mA | Normal mode, external reference = 2.5 V, DAC at full scale, SPI static | 8 |
| Junction-to-ambient thermal resistance (DGS VSSOP 10 pins) | RθJA |  | 170.1 |  | °C/W |  | 5 |
| Junction-to-case (top) thermal resistance (DGS VSSOP 10 pins) | RθJC(top) |  | 60.5 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance (DGS VSSOP 10 pins) | RθJB |  | 92.6 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter (DGS VSSOP 10 pins) | ΨJT |  | 7.8 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter (DGS VSSOP 10 pins) | ΨJB |  | 90.7 |  | °C/W |  | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs |  | Use a hold capacitor that has high insulation resistance, low temperature coefficient, and low dielectric absorption. Low temperature coefficient NP0/C0G ceramic capacitors are a great choice for this | 35 |

## CAD (KiCad official)

- Symbol: `DAC70501MDGSR`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `dac70501mdgsr-etched.step` / `dac70501mdgsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac70501mdgsr.step` / `dac70501mdgsr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac70501.pdf) (52 pp, sha256 `51dcb60423765d25`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dac70501mdgsr-datasheet.pdf)