component
DAC6571IDBVT
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DAC6571IDBVT
Texas Instruments · Digital To Analog Converters (DACs) · SOT-23-6
DAC6571IDBVT from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output voltage from the DAC, swinging from 0 V to VDD. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Analog voltage supply input, specified from +2.7 V to +5.5 V. |
| 4 | SDA | bidirectional | Serial data input for the I2C two-wire interface, operating at clock rates up to 3.4 MBPS. |
| 5 | SCL | input | Serial clock input for the I2C two-wire interface, operating at clock rates up to 3.4 MBPS. |
| 6 | A0 | input | Device address select, allowing up to two DAC6571 devices to share the same data bus. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Data Converters |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | 6 | V | 2 | ||
| Digital input voltage to GND | -0.3 | V | max printed as +VDD + 0.3 V | 2 | |||
| VOUT to GND | VOUT | -0.3 | V | max printed as +VDD + 0.3 V | 2 | ||
| Operating temperature range | TA | -40 | 105 | °C | 2 | ||
| Storage temperature range | -65 | 150 | °C | 2 | |||
| Junction temperature range (TJ max) | TJ | 150 | °C | 2 | |||
| Thermal impedance | RθJA | 240 | °C/W | 2 | |||
| Lead temperature, soldering vapor phase | 215 | °C | Vapor phase (60 s) | 2 | |||
| Lead temperature, soldering infrared | 220 | °C | Infrared (15 s) | 2 | |||
| Supply voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Relative accuracy | -2 | 2 | LSB | 3 | |||
| Differential nonlinearity | -0.5 | 0.5 | LSB | Assured monotonic by design | 3 | ||
| Zero code error | 5 | 20 | mV | 3 | |||
| Full-scale error | -0.15 | -1.25 | % of FSR | All ones loaded to DAC register | 3 | ||
| Gain error | -1.25 | 1.25 | % of FSR | 3 | |||
| Zero code error drift | -7 | 7 | µV/°C | 3 | |||
| Gain temperature coefficient | -3 | 3 | ppm of FSR/°C | 3 | |||
| Output voltage range | VOUT | 0 | V | max printed as VDD | 3 | ||
| Output voltage settling time | 7 | 9 | µs | 1/4 scale to 3/4 scale change (400H to C00H); RL = ∞ | 3 | ||
| Slew rate | 1 | V/µs | RL = ∞ | 3 | |||
| Capacitive load stability | CL | 470 | pF | RL = ∞ | 3 | ||
| Capacitive load stability | CL | 1000 | pF | RL = 2 kΩ | 3 | ||
| Code change glitch impulse | 20 | nV-s | 1 LSB change around major carry | 3 | |||
| Digital feedthrough | 0.5 | nV-s | 3 | ||||
| DC output impedance | 1 | Ω | 3 | ||||
| Short-circuit current | 50 | mA | VDD = +5 V | 3 | |||
| Short-circuit current | 20 | mA | VDD = +3 V | 3 | |||
| Power-up time | 2.5 | µs | Coming out of power-down mode, VDD = +5 V | 3 | |||
| Power-up time | 5 | µs | Coming out of power-down mode, VDD = +3 V | 3 | |||
| Input current | -1 | 1 | µA | 3 | |||
| Input low voltage | VINL | 0.3 | V | VDD = +3 V; printed as 0.3 × VDD | 3 | ||
| Input high voltage | VINH | 0.7 | V | VDD = +5 V; printed as 0.7 × VDD | 3 | ||
| Pin capacitance | 3 | pF | 3 | ||||
| IDD (normal operation) | IDD | 155 | 200 | µA | VDD = +3.6 V to +5.5 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 3 | |
| IDD (normal operation) | IDD | 125 | 160 | µA | VDD = +2.7 V to +3.6 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 3 | |
| IDD (all power-down modes) | IDD | 0.2 | 1 | µA | VDD = +3.6 V to +5.5 V; VIH = VDD and VIL = GND | 3 | |
| IDD (all power-down modes) | IDD | 0.05 | 1 | µA | VDD = +2.7 V to +3.6 V; VIH = VDD and VIL = GND | 3 | |
| Power efficiency IOUT/IDD | 93 | % | ILOAD = 2 mA, VDD = +5 V | 3 | |||
| SCL clock frequency, standard mode | fSCL | 100 | kHz | Standard mode | 4 | ||
| SCL clock frequency, fast mode | fSCL | 400 | kHz | Fast mode | 4 | ||
| SCL clock frequency, high-speed mode | fSCL | 3.4 | MHz | High-speed mode, CB = 100 pF max | 4 | ||
| SCL clock frequency, high-speed mode | fSCL | 1.7 | MHz | High-speed mode, CB = 400 pF max | 4 | ||
| Data hold time | tHD; tDAT | 0 | 3.45 | µs | Standard mode | 4 | |
| Data hold time | tHD; tDAT | 0 | 0.9 | µs | Fast mode | 4 | |
| Data setup time | tSU; tDAT | 250 | ns | Standard mode | 4 | ||
| Data setup time | tSU; tDAT | 100 | ns | Fast mode | 4 | ||
| Data setup time | tSU; tDAT | 10 | ns | High-speed mode | 4 | ||
| Bus free time between STOP and START | tBUF | 4.7 | µs | Standard mode | 4 | ||
| Bus free time between STOP and START | tBUF | 1.3 | µs | Fast mode | 4 | ||
| Setup time for STOP condition | tSU; tSTO | 4 | µs | Standard mode | 5 | ||
| Capacitive load for SDA and SCL | CB | 400 | pF | 5 |
CAD (KiCad official)
- Symbol:
DAC6571IDBVT - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
dac6571idbvt-etched.step/dac6571idbvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac6571idbvt.step/dac6571idbvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
aa2db9271760619b, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC6571IDBVT
**Texas Instruments** · Digital To Analog Converters (DACs) · SOT-23-6
DAC6571IDBVT from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output voltage from the DAC, swinging from 0 V to VDD. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Analog voltage supply input, specified from +2.7 V to +5.5 V. |
| 4 | SDA | bidirectional | Serial data input for the I2C two-wire interface, operating at clock rates up to 3.4 MBPS. |
| 5 | SCL | input | Serial clock input for the I2C two-wire interface, operating at clock rates up to 3.4 MBPS. |
| 6 | A0 | input | Device address select, allowing up to two DAC6571 devices to share the same data bus. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Data Converters |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | | 6 | V | | 2 |
| Digital input voltage to GND | | -0.3 | | | V | max printed as +VDD + 0.3 V | 2 |
| VOUT to GND | VOUT | -0.3 | | | V | max printed as +VDD + 0.3 V | 2 |
| Operating temperature range | TA | -40 | | 105 | °C | | 2 |
| Storage temperature range | | -65 | | 150 | °C | | 2 |
| Junction temperature range (TJ max) | TJ | | | 150 | °C | | 2 |
| Thermal impedance | RθJA | | 240 | | °C/W | | 2 |
| Lead temperature, soldering vapor phase | | | | 215 | °C | Vapor phase (60 s) | 2 |
| Lead temperature, soldering infrared | | | | 220 | °C | Infrared (15 s) | 2 |
| Supply voltage | VDD | 2.7 | | 5.5 | V | | 3 |
| Relative accuracy | | -2 | | 2 | LSB | | 3 |
| Differential nonlinearity | | -0.5 | | 0.5 | LSB | Assured monotonic by design | 3 |
| Zero code error | | | 5 | 20 | mV | | 3 |
| Full-scale error | | | -0.15 | -1.25 | % of FSR | All ones loaded to DAC register | 3 |
| Gain error | | -1.25 | | 1.25 | % of FSR | | 3 |
| Zero code error drift | | -7 | | 7 | µV/°C | | 3 |
| Gain temperature coefficient | | -3 | | 3 | ppm of FSR/°C | | 3 |
| Output voltage range | VOUT | 0 | | | V | max printed as VDD | 3 |
| Output voltage settling time | | | 7 | 9 | µs | 1/4 scale to 3/4 scale change (400H to C00H); RL = ∞ | 3 |
| Slew rate | | | 1 | | V/µs | RL = ∞ | 3 |
| Capacitive load stability | CL | | | 470 | pF | RL = ∞ | 3 |
| Capacitive load stability | CL | | | 1000 | pF | RL = 2 kΩ | 3 |
| Code change glitch impulse | | | 20 | | nV-s | 1 LSB change around major carry | 3 |
| Digital feedthrough | | | 0.5 | | nV-s | | 3 |
| DC output impedance | | | 1 | | Ω | | 3 |
| Short-circuit current | | | | 50 | mA | VDD = +5 V | 3 |
| Short-circuit current | | | | 20 | mA | VDD = +3 V | 3 |
| Power-up time | | | 2.5 | | µs | Coming out of power-down mode, VDD = +5 V | 3 |
| Power-up time | | | 5 | | µs | Coming out of power-down mode, VDD = +3 V | 3 |
| Input current | | -1 | | 1 | µA | | 3 |
| Input low voltage | VINL | | | 0.3 | V | VDD = +3 V; printed as 0.3 × VDD | 3 |
| Input high voltage | VINH | 0.7 | | | V | VDD = +5 V; printed as 0.7 × VDD | 3 |
| Pin capacitance | | | 3 | | pF | | 3 |
| IDD (normal operation) | IDD | | 155 | 200 | µA | VDD = +3.6 V to +5.5 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 3 |
| IDD (normal operation) | IDD | | 125 | 160 | µA | VDD = +2.7 V to +3.6 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 3 |
| IDD (all power-down modes) | IDD | | 0.2 | 1 | µA | VDD = +3.6 V to +5.5 V; VIH = VDD and VIL = GND | 3 |
| IDD (all power-down modes) | IDD | | 0.05 | 1 | µA | VDD = +2.7 V to +3.6 V; VIH = VDD and VIL = GND | 3 |
| Power efficiency IOUT/IDD | | | 93 | | % | ILOAD = 2 mA, VDD = +5 V | 3 |
| SCL clock frequency, standard mode | fSCL | | | 100 | kHz | Standard mode | 4 |
| SCL clock frequency, fast mode | fSCL | | | 400 | kHz | Fast mode | 4 |
| SCL clock frequency, high-speed mode | fSCL | | | 3.4 | MHz | High-speed mode, CB = 100 pF max | 4 |
| SCL clock frequency, high-speed mode | fSCL | | | 1.7 | MHz | High-speed mode, CB = 400 pF max | 4 |
| Data hold time | tHD; tDAT | 0 | | 3.45 | µs | Standard mode | 4 |
| Data hold time | tHD; tDAT | 0 | | 0.9 | µs | Fast mode | 4 |
| Data setup time | tSU; tDAT | | | 250 | ns | Standard mode | 4 |
| Data setup time | tSU; tDAT | | | 100 | ns | Fast mode | 4 |
| Data setup time | tSU; tDAT | | | 10 | ns | High-speed mode | 4 |
| Bus free time between STOP and START | tBUF | | | 4.7 | µs | Standard mode | 4 |
| Bus free time between STOP and START | tBUF | | | 1.3 | µs | Fast mode | 4 |
| Setup time for STOP condition | tSU; tSTO | | | 4 | µs | Standard mode | 5 |
| Capacitive load for SDA and SCL | CB | | | 400 | pF | | 5 |
## CAD (KiCad official)
- Symbol: `DAC6571IDBVT`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `dac6571idbvt-etched.step` / `dac6571idbvt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac6571idbvt.step` / `dac6571idbvt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac6571.pdf) (26 pp, sha256 `aa2db9271760619b`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac6571idbvt-datasheet.pdf)