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DAC61416RHAR

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Texas Instruments Digital To Analog Converters (DAC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DAC61416RHAR

Texas Instruments · Digital To Analog Converters (DAC) · VQFN-40-EP(6x6)

DAC61416RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT0 output Channel 0 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
2 OUT1 output Channel 1 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
3 OUT2 output Channel 2 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
4 OUT3 output Channel 3 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
5 OUT4 output Channel 4 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
6 OUT5 output Channel 5 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
7 OUT6 output Channel 6 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
8 OUT7 output Channel 7 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
9 VIO power_in I/O supply voltage, 1.7 V to 5.5 V, which sets the logic level of the digital inputs and outputs.
10 GND power_in Ground reference point for all circuits in the device.
11 SDO output Serial interface data output, enabled by setting the SDO-EN bit; data shifts out on the SCLK rising or falling edge as selected by the FSDO bit (default rising edge).
12 SCLK input Serial interface clock input for the SPI-compatible 4-wire interface, rated to 50 MHz.
13 SDI input Serial data input, with data shifted into the input shift register on each falling edge of SCLK.
14 CS input Active-low serial data enable and frame-sync input; the serial interface input shift register is enabled while CS is low.
15 TOGGLE0 input Toggle control input 0; logic low loads DAC output from register A and logic high loads it from register B, and it must be tied to GND if unused.
16 TOGGLE1 input Toggle control input 1; logic low loads DAC output from register A and logic high loads it from register B, and it must be tied to GND if unused.
17 TOGGLE2 input Toggle control input 2; logic low loads DAC output from register A and logic high loads it from register B, and it must be tied to GND if unused.
18 LDAC input Active-low synchronous update input; when low, all channels configured for synchronous mode update simultaneously, and it must be tied to VIO if unused.
19 RESET input Active-low hardware reset input; a logic low of at least 500 ns starts a power-on-reset event.
20 CLR input Active-low clear input; a logic low clears all DAC outputs to their clear code regardless of sync settings, and it must be tied to VIO if unused.
21 ALMOUT output Open-drain alarm output that requires an external 10 kΩ pull-up resistor to a voltage not greater than VIO.
22 TEMPOUT output Unbuffered analog temperature monitor output with a sensor gain of -4 mV/°C and a 1.34 V output at 0 °C.
23 OUT8 output Channel 8 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
24 OUT9 output Channel 9 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
25 OUT10 output Channel 10 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
26 OUT11 output Channel 11 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
27 OUT12 output Channel 12 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
28 OUT13 output Channel 13 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
29 OUT14 output Channel 14 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
30 OUT15 output Channel 15 buffered analog DAC output, software-configurable to ±20 V, ±10 V, ±5 V, ±2.5 V, 0-40 V, 0-20 V, 0-10 V or 0-5 V full-scale ranges.
31 VCC power_in Positive analog supply for the output amplifiers, 9 V to 41.5 V.
32 VSS power_in Negative analog supply for the output amplifiers, -21.5 V to 0 V.
33 REF bidirectional Reference input when using an external reference, or reference output when using the internal 2.5 V reference; connect a 150 nF capacitor to GND.
34 REFCMP bidirectional Reference compensation capacitor connection; connect a 330 pF capacitor between REFCMP and REFGND.
35 REFGND power_in Ground reference point for the internal reference.
36 GND power_in Ground reference point for all circuits in the device.
37 VAA power_in Analog supply voltage, 4.5 V to 5.5 V, which must be at the same potential as VDD.
38 VDD power_in Digital supply voltage, 4.5 V to 5.5 V, which must be at the same potential as VAA.
39 VSS power_in Negative analog supply for the output amplifiers, -21.5 V to 0 V.
40 VCC power_in Positive analog supply for the output amplifiers, 9 V to 41.5 V.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Data Acquisition
Pins 41

CAD (KiCad official)

  • Symbol: DAC61416RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: dac61416rhar-etched.step / dac61416rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac61416rhar.step / dac61416rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 78fbb0be664f4e12, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF