component
DAC61401PWR
Public Made by Adomby adom
Texas Instruments , TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Publish 0.1.0
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DAC61401PWR
Texas Instruments · IC · TSSOP-20
DAC61401PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREFIO | bidirectional | Internal reference output or external reference input; connect a 150nF capacitor to ground. |
| 2 | VREFGND | input | Reference ground, connects to 0V. |
| 3 | AVSS | power_in | Negative analog power supply, specified at -21.5V to 0V to GND in recommended operating conditions. |
| 4 | NC | unconnected | Must be left unconnected, pin floating. |
| 5 | AVDD | power_in | Positive analog power supply, specified at 4.5V to 41.5V to GND in recommended operating conditions. |
| 6 | NC | unconnected | Must be left unconnected, pin floating. |
| 7 | CCOMP | input | External compensation capacitor connection for VOUT; a 470pF typical capacitor improves stability with loads up to 1μF at the cost of increased settling time. |
| 8 | NC | unconnected | Must be left unconnected, pin floating. |
| 9 | VOUT | output | DAC voltage output pin. |
| 10 | VSENSEP | input | Sense pin for the positive voltage output load connection. |
| 11 | VSENSEN | input | Connect to 0V. |
| 12 | FAULT | output | Open-drain fault output that goes low when a fault condition is detected; requires an external 10kΩ pullup resistor. |
| 13 | SDO | output | Serial data output, with data valid on the rising or falling edge of SCLK as set by FSDO; high-impedance when SYNC is high. |
| 14 | SCLK | input | SPI serial clock input supporting rates up to 50MHz, with Schmitt-trigger logic input. |
| 15 | SDIN | input | Serial data input, clocked into the register on the falling edge of SCLK, with Schmitt-trigger logic input. |
| 16 | SYNC | input | Active-low SPI chip select; data is not clocked into the shift register unless SYNC is low. |
| 17 | IOVDD | power_in | IO pin power supply, specified at 1.7V to 5.5V to GND. |
| 18 | NC | unconnected | Must be left unconnected, pin floating. |
| 19 | GND | power_in | Digital and analog ground, connects to 0V. |
| 20 | VDD | power_in | Digital and analog power supply, specified at 4.5V to 5.5V to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | 6 | V | 4 | ||
| IOVDD to GND | IOVDD | -0.3 | 6 | V | 4 | ||
| AVDD to GND | AVDD | -0.3 | 44 | V | 4 | ||
| AVSS to GND | AVSS | -22 | 0.3 | V | 4 | ||
| AVDD to AVSS | -0.3 | 44 | V | 4 | |||
| VREFGND / VSENSEN to GND | -0.3 | 0.3 | V | 4 | |||
| FAULT to GND | -0.3 | 6 | V | 4 | |||
| Input current into any digital pin | -10 | 10 | mA | SCLK, SDIN, SDO, SYNC | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -60 | 150 | °C | 4 | ||
| VDD to GND | VDD | 4.5 | 5.5 | V | 4 | ||
| IOVDD to GND | IOVDD | 1.7 | 5.5 | V | 4 | ||
| AVDD to GND | AVDD | 4.5 | 41.5 | V | 4 | ||
| AVSS to GND | AVSS | -21.5 | 0 | V | 4 | ||
| AVDD to AVSS | 4.5 | 43 | V | 4 | |||
| Operating ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 83.1 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 21.7 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 36 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 0.9 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 35.4 | °C/W | PW (TSSOP) 20 pins | 5 | ||
| Relative accuracy | INL | -1 | 1 | LSB | DAC61401 | 5 | |
| Differential nonlinearity | DNL | -1 | 0.3 | 1 | LSB | 5 | |
| Total unadjusted error | TUE | -0.09 | 0.09 | %FSR | Unipolar ranges, AVSS = 0V | 5 | |
| Total unadjusted error | TUE | -0.07 | 0.07 | %FSR | Unipolar ranges, AVSS = 0V, 0°C ≤ TA ≤ 50°C | 5 | |
| Total unadjusted error | TUE | -0.095 | 0.095 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Offset error | OE | -0.05 | 0.05 | %FSR | Unipolar ranges, AVSS = 0V; Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Zero-code error | ZCE | 0.15 | %FSR | Unipolar ranges, AVSS = 0V | 5 | ||
| Zero-code error | ZCE | 0.05 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | ||
| Full-scale error | FSE | -0.08 | 0.08 | %FSR | Unipolar ranges, AVSS = 0V; Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Gain error | GE | -0.075 | 0.075 | %FSR | Unipolar ranges, AVSS = 0V | 5 | |
| Bipolar gain error | BPGE | -0.065 | 0.065 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Bipolar zero (midscale) error | BPZE | -0.04 | 0.04 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | |
| Capacitive load | CL | 0 | 2 | nF | RLOAD = open, CCOMP pin left floating | 6 | |
| Reference input voltage | VREFIO | 2.49 | 2.5 | 2.51 | V | 8 | |
| Reference output voltage | VREFO | 2.4975 | 2.5025 | V | TA = 25°C | 8 | |
| Reference output drift | 5 | 10 | ppm/°C | 8 | |||
| SDO low-level output voltage | VOL | 0.4 | V | SDO load current = 0.2mA | 9 | ||
| FAULT low-level output voltage | 0.4 | V | FAULT load current = 10mA | 9 | |||
| Digital input current | -2 | 2 | µA | 9 | |||
| IOVDD supply current | IIOVDD | 10 | 120 | µA | SCLK toggling at 1MHz | 9 | |
| SCLK frequency | fSCLK | 25 | MHz | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SCLK high time | tSCLKHIGH | 20 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SCLK low time | tSCLKLOW | 20 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SDIN setup | tSDIS | 10 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SDIN hold | tSDIH | 10 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SYNC to SCLK falling edge setup | tCSS | 30 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SCLK falling edge to SYNC rising edge | tCSH | 10 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SYNC high time | tCSHIGH | 50 | ns | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| Sequential DAC update wait time | tDACWAIT | 2.4 | µs | Write, IOVDD = 1.7V to 2.7V | 10 | ||
| SCLK frequency | fSCLK | 50 | MHz | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SCLK high time | tSCLKHIGH | 10 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SCLK low time | tSCLKLOW | 10 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SDIN setup | tSDIS | 5 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SDIN hold | tSDIH | 5 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SYNC to SCLK falling edge setup | tCSS | 15 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SCLK falling edge to SYNC rising edge | tCSH | 5 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| SYNC high time | tCSHIGH | 25 | ns | Write, IOVDD = 2.7V to 5.5V | 10 | ||
| Offset error temperature coefficient | OE-TC | 2 | ppmFSR/°C | Unipolar ranges, AVSS = 0V; Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 | ||
| Gain error temperature coefficient | GE-TC | 2 | ppmFSR/°C | 5 | |||
| Full-scale error temperature coefficient | FSE-TC | 3 | ppmFSR/°C | 5 |
CAD (KiCad official)
- Symbol:
DAC61401PWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
dac61401pwr-etched.step/dac61401pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac61401pwr.step/dac61401pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
8d810beb78f170e9, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DAC61401PWR
**Texas Instruments** · IC · TSSOP-20
DAC61401PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREFIO | bidirectional | Internal reference output or external reference input; connect a 150nF capacitor to ground. |
| 2 | VREFGND | input | Reference ground, connects to 0V. |
| 3 | AVSS | power_in | Negative analog power supply, specified at -21.5V to 0V to GND in recommended operating conditions. |
| 4 | NC | unconnected | Must be left unconnected, pin floating. |
| 5 | AVDD | power_in | Positive analog power supply, specified at 4.5V to 41.5V to GND in recommended operating conditions. |
| 6 | NC | unconnected | Must be left unconnected, pin floating. |
| 7 | CCOMP | input | External compensation capacitor connection for VOUT; a 470pF typical capacitor improves stability with loads up to 1μF at the cost of increased settling time. |
| 8 | NC | unconnected | Must be left unconnected, pin floating. |
| 9 | VOUT | output | DAC voltage output pin. |
| 10 | VSENSEP | input | Sense pin for the positive voltage output load connection. |
| 11 | VSENSEN | input | Connect to 0V. |
| 12 | FAULT | output | Open-drain fault output that goes low when a fault condition is detected; requires an external 10kΩ pullup resistor. |
| 13 | SDO | output | Serial data output, with data valid on the rising or falling edge of SCLK as set by FSDO; high-impedance when SYNC is high. |
| 14 | SCLK | input | SPI serial clock input supporting rates up to 50MHz, with Schmitt-trigger logic input. |
| 15 | SDIN | input | Serial data input, clocked into the register on the falling edge of SCLK, with Schmitt-trigger logic input. |
| 16 | SYNC | input | Active-low SPI chip select; data is not clocked into the shift register unless SYNC is low. |
| 17 | IOVDD | power_in | IO pin power supply, specified at 1.7V to 5.5V to GND. |
| 18 | NC | unconnected | Must be left unconnected, pin floating. |
| 19 | GND | power_in | Digital and analog ground, connects to 0V. |
| 20 | VDD | power_in | Digital and analog power supply, specified at 4.5V to 5.5V to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | | 6 | V | | 4 |
| IOVDD to GND | IOVDD | -0.3 | | 6 | V | | 4 |
| AVDD to GND | AVDD | -0.3 | | 44 | V | | 4 |
| AVSS to GND | AVSS | -22 | | 0.3 | V | | 4 |
| AVDD to AVSS | | -0.3 | | 44 | V | | 4 |
| VREFGND / VSENSEN to GND | | -0.3 | | 0.3 | V | | 4 |
| FAULT to GND | | -0.3 | | 6 | V | | 4 |
| Input current into any digital pin | | -10 | | 10 | mA | SCLK, SDIN, SDO, SYNC | 4 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -60 | | 150 | °C | | 4 |
| VDD to GND | VDD | 4.5 | | 5.5 | V | | 4 |
| IOVDD to GND | IOVDD | 1.7 | | 5.5 | V | | 4 |
| AVDD to GND | AVDD | 4.5 | | 41.5 | V | | 4 |
| AVSS to GND | AVSS | -21.5 | | 0 | V | | 4 |
| AVDD to AVSS | | 4.5 | | 43 | V | | 4 |
| Operating ambient temperature | TA | -40 | | 125 | °C | | 4 |
| Junction-to-ambient thermal resistance | RθJA | | 83.1 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 21.7 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-board thermal resistance | RθJB | | 36 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-top characterization parameter | ΨJT | | 0.9 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Junction-to-board characterization parameter | ΨJB | | 35.4 | | °C/W | PW (TSSOP) 20 pins | 5 |
| Relative accuracy | INL | -1 | | 1 | LSB | DAC61401 | 5 |
| Differential nonlinearity | DNL | -1 | 0.3 | 1 | LSB | | 5 |
| Total unadjusted error | TUE | -0.09 | | 0.09 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Total unadjusted error | TUE | -0.07 | | 0.07 | %FSR | Unipolar ranges, AVSS = 0V, 0°C ≤ TA ≤ 50°C | 5 |
| Total unadjusted error | TUE | -0.095 | | 0.095 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Offset error | OE | -0.05 | | 0.05 | %FSR | Unipolar ranges, AVSS = 0V; Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Zero-code error | ZCE | | | 0.15 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Zero-code error | ZCE | | | 0.05 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Full-scale error | FSE | -0.08 | | 0.08 | %FSR | Unipolar ranges, AVSS = 0V; Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Gain error | GE | -0.075 | | 0.075 | %FSR | Unipolar ranges, AVSS = 0V | 5 |
| Bipolar gain error | BPGE | -0.065 | | 0.065 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Bipolar zero (midscale) error | BPZE | -0.04 | | 0.04 | %FSR | Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Capacitive load | CL | 0 | | 2 | nF | RLOAD = open, CCOMP pin left floating | 6 |
| Reference input voltage | VREFIO | 2.49 | 2.5 | 2.51 | V | | 8 |
| Reference output voltage | VREFO | 2.4975 | | 2.5025 | V | TA = 25°C | 8 |
| Reference output drift | | | 5 | 10 | ppm/°C | | 8 |
| SDO low-level output voltage | VOL | | | 0.4 | V | SDO load current = 0.2mA | 9 |
| FAULT low-level output voltage | | | | 0.4 | V | FAULT load current = 10mA | 9 |
| Digital input current | | -2 | | 2 | µA | | 9 |
| IOVDD supply current | IIOVDD | | 10 | 120 | µA | SCLK toggling at 1MHz | 9 |
| SCLK frequency | fSCLK | | | 25 | MHz | Write, IOVDD = 1.7V to 2.7V | 10 |
| SCLK high time | tSCLKHIGH | 20 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| SCLK low time | tSCLKLOW | 20 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| SDIN setup | tSDIS | 10 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| SDIN hold | tSDIH | 10 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| SYNC to SCLK falling edge setup | tCSS | 30 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| SCLK falling edge to SYNC rising edge | tCSH | 10 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| SYNC high time | tCSHIGH | 50 | | | ns | Write, IOVDD = 1.7V to 2.7V | 10 |
| Sequential DAC update wait time | tDACWAIT | 2.4 | | | µs | Write, IOVDD = 1.7V to 2.7V | 10 |
| SCLK frequency | fSCLK | | | 50 | MHz | Write, IOVDD = 2.7V to 5.5V | 10 |
| SCLK high time | tSCLKHIGH | 10 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| SCLK low time | tSCLKLOW | 10 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| SDIN setup | tSDIS | 5 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| SDIN hold | tSDIH | 5 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| SYNC to SCLK falling edge setup | tCSS | 15 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| SCLK falling edge to SYNC rising edge | tCSH | 5 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| SYNC high time | tCSHIGH | 25 | | | ns | Write, IOVDD = 2.7V to 5.5V | 10 |
| Offset error temperature coefficient | OE-TC | | 2 | | ppmFSR/°C | Unipolar ranges, AVSS = 0V; Bipolar ranges, -21.5V ≤ AVSS < 0V | 5 |
| Gain error temperature coefficient | GE-TC | | 2 | | ppmFSR/°C | | 5 |
| Full-scale error temperature coefficient | FSE-TC | | 3 | | ppmFSR/°C | | 5 |
## CAD (KiCad official)
- Symbol: `DAC61401PWR`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `dac61401pwr-etched.step` / `dac61401pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac61401pwr.step` / `dac61401pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dac61401.pdf) (55 pp, sha256 `8d810beb78f170e9`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dac61401pwr-datasheet.pdf)