component
DAC60004IPW
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# DAC60004IPW++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-14++DAC60004IPW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | LDAC | input | Load DAC pin (active low) for simultaneous update of all DAC outputs. |+| 2 | SYNC | input | Serial interface synchronization input (active low); falling edge starts operation cycle, rising edge before 32nd SCLK falling edge aborts write sequence. |+| 3 | VDD | power_in | Positive power supply voltage (2.7 V to 5.5 V). |+| 4 | VOUTA | output | Analog output of channel A with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |+| 5 | VOUTC | output | Analog output of channel C with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |+| 6 | POR | input | Power-on-reset configuration input; connect to GND for zero scale startup or to VDD for midscale startup. |+| 7 | REFIN | input | Voltage reference input for all channels (2.2 V to VDD or VDD-0.2 V depending on supply level) with 30 kΩ typical constant input impedance. |+| 8 | SDO | tri_state | Serial interface digital output for readback and daisy chaining; Hi-Z when DSDO bit is 0 (default) or when SYNC is high. |+| 9 | CLR | input | Clear DAC pin (falling edge sensitive) to clear all DAC buffers and latches to zero scale, midscale, or full-scale per clear mode register. |+| 10 | VOUTD | output | Analog output of channel D with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |+| 11 | VOUTB | output | Analog output of channel B with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |+| 12 | GND | power_in | Ground, power return path. |+| 13 | SDIN | input | Serial interface digital input for 32-bit shift register, operating at up to 50 MHz clock rate. |+| 14 | SCLK | input | Serial interface shift clock input, up to 50 MHz; input data sampled on falling edges. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `DAC60004IPW`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `dac60004ipw-etched.step` / `dac60004ipw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac60004ipw.step` / `dac60004ipw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac70004) (44 pp, sha256 `17e505dbbc67542a`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac60004ipw-datasheet.pdf)
page.jsonadded+234@@ -0,0 +1,234 @@+{+ "slug": "dac60004ipw",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac60004ipw",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac60004ipw.kicad_sym",+ "dac60004ipw.kicad_mod",+ "dac60004ipw.glb",+ "dac60004ipw.step",+ "dac60004ipw.lbr",+ "docs/hero.png",+ "docs/dac60004ipw-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac60004ipw-hero.glb",+ "dac60004ipw-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC60004IPW",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac70004",+ "parts": {+ "symbol": "dac60004ipw.kicad_sym",+ "footprint": "dac60004ipw.kicad_mod",+ "model_3d": "dac60004ipw-hero.glb",+ "model_3d_plain": "dac60004ipw.glb",+ "model_3d_step": "dac60004ipw-etched.step",+ "model_3d_step_plain": "dac60004ipw.step",+ "lbr": "dac60004ipw.lbr"+ },+ "distributor_links": {+ "lcsc": "C1554723",+ "digikey": "DAC60004IPW-ND",+ "mouser": "595-DAC60004IPW"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T08:29:28Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "DAC60004IPW-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DAC60004IPW",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "LDAC",+ "type": "input",+ "description": "Load DAC pin (active low) for simultaneous update of all DAC outputs."+ },+ {+ "number": "2",+ "name": "SYNC",+ "type": "input",+ "description": "Serial interface synchronization input (active low); falling edge starts operation cycle, rising edge before 32nd SCLK falling edge aborts write sequence."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive power supply voltage (2.7 V to 5.5 V)."+ },+ {+ "number": "4",+ "name": "VOUTA",+ "type": "output",+ "description": "Analog output of channel A with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical."+ },+ {+ "number": "5",+ "name": "VOUTC",+ "type": "output",+ "description": "Analog output of channel C with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical."+ },+ {+ "number": "6",+ "name": "POR",+ "type": "input",+ "description": "Power-on-reset configuration input; connect to GND for zero scale startup or to VDD for midscale startup."+ },+ {+ "number": "7",+ "name": "REFIN",+ "type": "input",+ "description": "Voltage reference input for all channels (2.2 V to VDD or VDD-0.2 V depending on supply level) with 30 kΩ typical constant input impedance."+ },+ {+ "number": "8",+ "name": "SDO",+ "type": "tri_state",+ "description": "Serial interface digital output for readback and daisy chaining; Hi-Z when DSDO bit is 0 (default) or when SYNC is high."+ },+ {+ "number": "9",+ "name": "CLR",+ "type": "input",+ "description": "Clear DAC pin (falling edge sensitive) to clear all DAC buffers and latches to zero scale, midscale, or full-scale per clear mode register."+ },+ {+ "number": "10",+ "name": "VOUTD",+ "type": "output",+ "description": "Analog output of channel D with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical."+ },+ {+ "number": "11",+ "name": "VOUTB",+ "type": "output",+ "description": "Analog output of channel B with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground, power return path."+ },+ {+ "number": "13",+ "name": "SDIN",+ "type": "input",+ "description": "Serial interface digital input for 32-bit shift register, operating at up to 50 MHz clock rate."+ },+ {+ "number": "14",+ "name": "SCLK",+ "type": "input",+ "description": "Serial interface shift clock input, up to 50 MHz; input data sampled on falling edges."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 16,+ "cost_usd": 0.1525,+ "at": "2026-10-07T08:29:12"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac70004",+ "pages": 44,+ "sha256": "17e505dbbc67542a",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac60004ipw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac60004ipw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "400acddbbe003b27aae7b4d8518cee94c2b0e99e42d081b0480e0daf67860ad8",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}