component
DAC60004IPW
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC60004IPW
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-14
DAC60004IPW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Load DAC pin (active low) for simultaneous update of all DAC outputs. |
| 2 | SYNC | input | Serial interface synchronization input (active low); falling edge starts operation cycle, rising edge before 32nd SCLK falling edge aborts write sequence. |
| 3 | VDD | power_in | Positive power supply voltage (2.7 V to 5.5 V). |
| 4 | VOUTA | output | Analog output of channel A with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |
| 5 | VOUTC | output | Analog output of channel C with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |
| 6 | POR | input | Power-on-reset configuration input; connect to GND for zero scale startup or to VDD for midscale startup. |
| 7 | REFIN | input | Voltage reference input for all channels (2.2 V to VDD or VDD-0.2 V depending on supply level) with 30 kΩ typical constant input impedance. |
| 8 | SDO | tri_state | Serial interface digital output for readback and daisy chaining; Hi-Z when DSDO bit is 0 (default) or when SYNC is high. |
| 9 | CLR | input | Clear DAC pin (falling edge sensitive) to clear all DAC buffers and latches to zero scale, midscale, or full-scale per clear mode register. |
| 10 | VOUTD | output | Analog output of channel D with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |
| 11 | VOUTB | output | Analog output of channel B with voltage range 0 V to REFIN and slew rate of 1.5 V/µs typical. |
| 12 | GND | power_in | Ground, power return path. |
| 13 | SDIN | input | Serial interface digital input for 32-bit shift register, operating at up to 50 MHz clock rate. |
| 14 | SCLK | input | Serial interface shift clock input, up to 50 MHz; input data sampled on falling edges. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
DAC60004IPW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
dac60004ipw-etched.step/dac60004ipw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac60004ipw.step/dac60004ipw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
17e505dbbc67542a, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).