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DAC5681ZIRGCR

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Texas Instruments Digital To Analog Converters (DACs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DAC5681ZIRGCR

Texas Instruments · Digital To Analog Converters (DACs) · VQFN-64-EP(9x9)

DAC5681ZIRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKVDD power_in Internal clock buffer supply, 1.8 V nominal (1.7 V to 1.9 V recommended operating range).
2 CLKIN input Positive external DAC clock input, self-biased to about CLKVDD/2; with the PLL enabled it is the lower-frequency reference, and with the PLL disabled it clocks the DAC directly up to 1 GHz.
3 CLKINC input Complementary external clock input to CLKIN, used as a differential pair with CLKIN.
4 GND power_in Ground for the AVDD, DVDD, and IOVDD supplies; pin 4 and the exposed thermal pad on the package bottom are both ground.
5 SYNCP input Positive LVDS SYNC input with internal 100-Ω termination; by default SYNCP/N must be logic 1 to enable a DAC analog output.
6 SYNCN input Negative LVDS SYNC input, complementary to SYNCP, with internal 100-Ω termination.
7 D15P input Positive LVDS input data bit 15 (MSB), double data rate with two samples per DCLKP/N cycle and an internal 100-Ω termination across the pair.
8 D15N input Negative LVDS input data bit 15 (MSB), complementary to D15P with internal 100-Ω termination.
9 IOVDD power_in Digital I/O supply for RESETB, SCLK, SDENB, SDIO, and SDO, 3.0 V to 3.6 V (3.3 V nominal).
10 DVDD power_in Digital supply, 1.7 V to 1.9 V (1.8 V nominal).
11 D14P input Positive LVDS input data bit 14 with internal 100-Ω termination, double data rate relative to DCLKP/N.
12 D14N input Negative LVDS input data bit 14, complementary to D14P with internal 100-Ω termination.
13 D13P input Positive LVDS input data bit 13 with internal 100-Ω termination, double data rate relative to DCLKP/N.
14 D13N input Negative LVDS input data bit 13, complementary to D13P with internal 100-Ω termination.
15 D12P input Positive LVDS input data bit 12 with internal 100-Ω termination, double data rate relative to DCLKP/N.
16 D12N input Negative LVDS input data bit 12, complementary to D12P with internal 100-Ω termination.
17 D11P input Positive LVDS input data bit 11 with internal 100-Ω termination, double data rate relative to DCLKP/N.
18 D11N input Negative LVDS input data bit 11, complementary to D11P with internal 100-Ω termination.
19 D10P input Positive LVDS input data bit 10 with internal 100-Ω termination, double data rate relative to DCLKP/N.
20 D10N input Negative LVDS input data bit 10, complementary to D10P with internal 100-Ω termination.
21 D9P input Positive LVDS input data bit 9 with internal 100-Ω termination, double data rate relative to DCLKP/N.
22 D9N input Negative LVDS input data bit 9, complementary to D9P with internal 100-Ω termination.
23 D8P input Positive LVDS input data bit 8 with internal 100-Ω termination, double data rate relative to DCLKP/N.
24 D8N input Negative LVDS input data bit 8, complementary to D8P with internal 100-Ω termination.
25 DCLKP input Positive LVDS data clock, self-biased to about DVDD/2 with no internal termination; requires an external 100-Ω resistor across the pair with 0.01-µF series capacitors.
26 DCLKN input Negative LVDS data clock, complementary to DCLKP, self-biased to about DVDD/2 with no internal termination.
27 D7P input Positive LVDS input data bit 7 with internal 100-Ω termination, double data rate relative to DCLKP/N.
28 D7N input Negative LVDS input data bit 7, complementary to D7P with internal 100-Ω termination.
29 D6P input Positive LVDS input data bit 6 with internal 100-Ω termination, double data rate relative to DCLKP/N.
30 D6N input Negative LVDS input data bit 6, complementary to D6P with internal 100-Ω termination.
31 D5P input Positive LVDS input data bit 5 with internal 100-Ω termination, double data rate relative to DCLKP/N.
32 D5N input Negative LVDS input data bit 5, complementary to D5P with internal 100-Ω termination.
33 D4P input Positive LVDS input data bit 4 with internal 100-Ω termination, double data rate relative to DCLKP/N.
34 D4N input Negative LVDS input data bit 4, complementary to D4P with internal 100-Ω termination.
35 D3P input Positive LVDS input data bit 3 with internal 100-Ω termination, double data rate relative to DCLKP/N.
36 D3N input Negative LVDS input data bit 3, complementary to D3P with internal 100-Ω termination.
37 D2P input Positive LVDS input data bit 2 with internal 100-Ω termination, double data rate relative to DCLKP/N.
38 D2N input Negative LVDS input data bit 2, complementary to D2P with internal 100-Ω termination.
39 DVDD power_in Digital supply, 1.7 V to 1.9 V (1.8 V nominal).
40 D1P input Positive LVDS input data bit 1 with internal 100-Ω termination, double data rate relative to DCLKP/N.
41 D1N input Negative LVDS input data bit 1, complementary to D1P with internal 100-Ω termination.
42 D0P input Positive LVDS input data bit 0 (LSB) with internal 100-Ω termination, double data rate relative to DCLKP/N.
43 D0N input Negative LVDS input data bit 0 (LSB), complementary to D0P with internal 100-Ω termination.
44 VFUSE power_in Digital supply, 1.8 V nominal; connect to DVDD for normal operation, and also used for factory fuse programming.
45 SDO output Unidirectional serial data output in 4-pin mode; high-impedance in 3-pin mode (default), optionally usable as a status output via CONFIG14 SDO_func_sel(2:0), with internal pulldown.
46 SDIO bidirectional Bidirectional serial data in 3-pin mode (default); becomes input-only in 4-pin mode (CONFIG5 sif4), with internal pulldown.
47 SCLK input Serial interface clock with internal pulldown; data is clocked into the device on the rising edge of SCLK.
48 SDENB input Active-low serial data enable, always an input to the DAC, with internal pullup.
49 RESETB input Active-low chip reset input with internal pullup; the chip is reset when this pin is low.
50 DVDD power_in Digital supply, 1.7 V to 1.9 V (1.8 V nominal).
51 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
52 IOUTA1 output DAC current output; offset-binary code 0x0000 gives full-scale current sink and the least positive voltage, and 0xFFFF gives 0 mA, with compliance of AVDD − 0.5 V to AVDD + 0.5 V.
53 IOUTA2 output Complementary DAC current output with opposite behavior to IOUTA1; code 0x0000 gives 0 mA sink and the most positive voltage.
54 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
55 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
56 EXTIO bidirectional Used as 1.2-V internal reference output when EXTLO is GND (requires 0.1-µF decoupling to AGND), or as external reference input when EXTLO is connected to AVDD.
57 BIASJ output Full-scale output current bias; connect a 960-Ω resistor to GND for 20-mA full-scale output current.
58 EXTLO output Reference configuration pin: connect to GND to select the internal reference or to AVDD to select an external reference.
59 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
60 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
61 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
62 AVDD power_in Analog supply, 3.0 V to 3.6 V (3.3 V nominal).
63 DVDD power_in Digital supply, 1.7 V to 1.9 V (1.8 V nominal).
64 LPF input PLL loop filter connection; may be left open if the clock-multiplying PLL is not used, in which case PLL_bypass and PLL_sleep should be set for reduced power.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category ADC/DAC/Data Conversion
Pins 65

CAD (KiCad official)

  • Symbol: DAC5681ZIRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: dac5681zirgcr-etched.step / dac5681zirgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac5681zirgcr.step / dac5681zirgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (59 pp, sha256 daf1e7beeeb08e7b, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF