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DAC5578SRGET

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Texas Instruments Digital To Analog Converters (DAC), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DAC5578SRGET

Texas Instruments · Digital To Analog Converters (DAC) · QFN-24-EP(4x4)

DAC5578SRGET from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not internally connected.
2 AVDD power_in Analog power-supply input, specified at 2.7 V to 5.5 V.
3 VOUTA output Analog output voltage from DAC A, with an output range of 0 to AVDD.
4 VOUTC output Analog output voltage from DAC C, with an output range of 0 to AVDD.
5 VOUTE output Analog output voltage from DAC E, with an output range of 0 to AVDD.
6 VOUTG output Analog output voltage from DAC G, with an output range of 0 to AVDD.
7 NC unconnected Not internally connected.
8 VREFIN input Positive reference input; external reference current is specified at 60 µA with AVDD = 2.7 V to 5.5 V.
9 RSTSEL input Reset select pin: RSTSEL high resets the device to mid-scale, and RSTSEL low resets it to zero-scale.
10 ADDR1 input 3-state address input used to set the device's two-wire (I2C) address.
11 ADDR0 input 3-state address input used to set the device's two-wire (I2C) address.
12 CLR input Asynchronous clear input.
13 VOUTH output Analog output voltage from DAC H, with an output range of 0 to AVDD.
14 VOUTF output Analog output voltage from DAC F, with an output range of 0 to AVDD.
15 VOUTD output Analog output voltage from DAC D, with an output range of 0 to AVDD.
16 VOUTB output Analog output voltage from DAC B, with an output range of 0 to AVDD.
17 GND power_in Ground reference point for all circuitry on the device.
18 NC unconnected Not internally connected.
19 SDA bidirectional Serial data line; bidirectional open-drain that must be connected to the supply through an external pull-up resistor.
20 SCL input Serial clock input, with data transfer at rates up to 3.4 MHz; Schmitt-trigger logic input.
21 TWOC input Twos complement select: high uses twos complement DAC register format, and low uses straight binary format.
22 LDAC input Load DACs control input for updating the DAC registers.
23 NC unconnected Not internally connected.
24 NC unconnected Not internally connected.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-24-EP(4x4)
Category Data Acquisition
Pins 25

CAD (KiCad official)

  • Symbol: DAC5578SRGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: dac5578srget-etched.step / dac5578srget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac5578srget.step / dac5578srget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 384236e44db678a7, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF