component
DAC53202RTER
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# DAC53202RTER++**Texas Instruments** · Digital To Analog Converters (DAC) · WQFN-16(3x3)++DAC53202RTER from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | FB0 | input | Voltage feedback pin for channel 0; in voltage-output mode connect to OUT0 for closed-loop amplifier output, and in current-output mode leave unconnected to minimize leakage current. |+| 2 | OUT0 | output | Analog output voltage from DAC channel 0. |+| 3 | NC | unconnected | No connection; leave the pin unconnected. |+| 4 | NC | unconnected | No connection; leave the pin unconnected. |+| 5 | GPIO/SDO | bidirectional | General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, or STATUS; for STATUS and SDO connect to IO voltage with an external pullup, if unused connect to VDD or AGND through an external resistor, and the pin can ramp up before VDD. |+| 6 | SCL/SYNC | output | I2C serial interface clock or SPI chip select input; must be connected to the IO voltage through an external pullup resistor and can ramp up before VDD. |+| 7 | A0/SDI | input | Address configuration pin for I2C (connect to VDD, AGND, SDA, or SCL) or serial data input for SPI; SDI needs no pullup or pulldown and the pin can ramp up before VDD. |+| 8 | SDA/SCLK | bidirectional | Bidirectional I2C serial data bus or SPI clock input; must be connected to the IO voltage through an external pullup resistor in I2C mode and can ramp up before VDD. |+| 9 | NC | unconnected | No connection; leave the pin unconnected. |+| 10 | NC | unconnected | No connection; leave the pin unconnected. |+| 11 | OUT1 | output | Analog output voltage from DAC channel 1. |+| 12 | FB1 | input | Voltage feedback pin for channel 1; in voltage-output mode connect to OUT1 for closed-loop amplifier output, and in current-output mode leave unconnected to minimize leakage current. |+| 13 | CAP | power_out | External bypass capacitor for the internal LDO; connect approximately 1.5 µF between CAP and AGND (CCAP range 0.5 µF to 15 µF per recommended operating conditions). |+| 14 | AGND | power_in | Ground reference point for all circuitry on the device. |+| 15 | VDD | power_in | Supply voltage (1.7 V to 5.5 V recommended, referenced to AGND). |+| 16 | VREF | power_in | External reference input; connect approximately 0.1 µF between VREF and AGND, use a pullup to VDD when the external reference is not used, and the pin must not ramp up before VDD. |+| 17 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-16(3x3) |+| Category | Data Acquisition |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `DAC53202RTER`+- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`+- 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)+- 3D model files: `dac53202rter-etched.step` / `dac53202rter-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac53202rter.step` / `dac53202rter.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904689959919616) (83 pp, sha256 `c5474701e67fa840`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac53202rter-datasheet.pdf)
page.jsonadded+254@@ -0,0 +1,254 @@+{+ "slug": "dac53202rter",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac53202rter",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac53202rter.kicad_sym",+ "dac53202rter.kicad_mod",+ "dac53202rter.glb",+ "dac53202rter.step",+ "dac53202rter.lbr",+ "docs/hero.png",+ "docs/dac53202rter-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac53202rter-hero.glb",+ "dac53202rter-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC53202RTER",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-16(3x3)",+ "pin_count": 17,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904689959919616",+ "parts": {+ "symbol": "dac53202rter.kicad_sym",+ "footprint": "dac53202rter.kicad_mod",+ "model_3d": "dac53202rter-hero.glb",+ "model_3d_plain": "dac53202rter.glb",+ "model_3d_step": "dac53202rter-etched.step",+ "model_3d_step_plain": "dac53202rter.step",+ "lbr": "dac53202rter.lbr"+ },+ "distributor_links": {+ "lcsc": "C5711651",+ "digikey": "296-DAC53202RTERTR-ND",+ "mouser": "595-DAC53202RTER"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T04:25:20Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DAC53202RTERTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DAC53202RTER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "FB0",+ "type": "input",+ "description": "Voltage feedback pin for channel 0; in voltage-output mode connect to OUT0 for closed-loop amplifier output, and in current-output mode leave unconnected to minimize leakage current."+ },+ {+ "number": "2",+ "name": "OUT0",+ "type": "output",+ "description": "Analog output voltage from DAC channel 0."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave the pin unconnected."+ },+ {+ "number": "4",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave the pin unconnected."+ },+ {+ "number": "5",+ "name": "GPIO/SDO",+ "type": "bidirectional",+ "description": "General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, or STATUS; for STATUS and SDO connect to IO voltage with an external pullup, if unused connect to VDD or AGND through an external resistor, and the pin can ramp up before VDD."+ },+ {+ "number": "6",+ "name": "SCL/SYNC",+ "type": "output",+ "description": "I2C serial interface clock or SPI chip select input; must be connected to the IO voltage through an external pullup resistor and can ramp up before VDD."+ },+ {+ "number": "7",+ "name": "A0/SDI",+ "type": "input",+ "description": "Address configuration pin for I2C (connect to VDD, AGND, SDA, or SCL) or serial data input for SPI; SDI needs no pullup or pulldown and the pin can ramp up before VDD."+ },+ {+ "number": "8",+ "name": "SDA/SCLK",+ "type": "bidirectional",+ "description": "Bidirectional I2C serial data bus or SPI clock input; must be connected to the IO voltage through an external pullup resistor in I2C mode and can ramp up before VDD."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave the pin unconnected."+ },+ {+ "number": "10",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave the pin unconnected."+ },+ {+ "number": "11",+ "name": "OUT1",+ "type": "output",+ "description": "Analog output voltage from DAC channel 1."+ },+ {+ "number": "12",+ "name": "FB1",+ "type": "input",+ "description": "Voltage feedback pin for channel 1; in voltage-output mode connect to OUT1 for closed-loop amplifier output, and in current-output mode leave unconnected to minimize leakage current."+ },+ {+ "number": "13",+ "name": "CAP",+ "type": "power_out",+ "description": "External bypass capacitor for the internal LDO; connect approximately 1.5 µF between CAP and AGND (CCAP range 0.5 µF to 15 µF per recommended operating conditions)."+ },+ {+ "number": "14",+ "name": "AGND",+ "type": "power_in",+ "description": "Ground reference point for all circuitry on the device."+ },+ {+ "number": "15",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage (1.7 V to 5.5 V recommended, referenced to AGND)."+ },+ {+ "number": "16",+ "name": "VREF",+ "type": "power_in",+ "description": "External reference input; connect approximately 0.1 µF between VREF and AGND, use a pullup to VDD when the external reference is not used, and the pin must not ramp up before VDD."+ },+ {+ "number": "17",+ "name": "Thermal Pad",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet's pin table lists SCL/SYNC as type 'Output', but the function described is an I2C seri; The exposed thermal pad is not a numbered pin in the datasheet (Table 5-1 lists it as 'Thermal Pad',; Pins 3, 4, 9 and 10 are listed as NC (no connection) and are included with type 'unconnected'.",+ "exposed pad 17 added from the footprint"+ ],+ "pages_sent": 9,+ "cost_usd": 0.058,+ "at": "2026-10-08T04:25:07"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904689959919616",+ "pages": 83,+ "sha256": "c5474701e67fa840",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac53202rter.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3,+ 3,+ 0.785+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac53202rter-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3,+ 3,+ 0.785+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "1ef991f3116fde25c57f6123bd0bf8783d0ed14854be6a991f4d9aa1258a2e45",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}