DAC3162IRGZR

{
  "slug": "dac3162irgzr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Digital To Analog Converters (DAC), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "dac3162irgzr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "dac3162irgzr.kicad_sym",
    "dac3162irgzr.kicad_mod",
    "dac3162irgzr.glb",
    "dac3162irgzr.step",
    "dac3162irgzr.lbr",
    "docs/hero.png",
    "docs/dac3162irgzr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dac3162irgzr-hero.glb",
    "dac3162irgzr-hero.overlay.json"
  ],
  "component": {
    "mpn": "DAC3162IRGZR",
    "manufacturer": "Texas Instruments",
    "package": "QFN-48-EP(7x7)",
    "pin_count": 49,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/dac3162",
    "parts": {
      "symbol": "dac3162irgzr.kicad_sym",
      "footprint": "dac3162irgzr.kicad_mod",
      "model_3d": "dac3162irgzr-hero.glb",
      "model_3d_plain": "dac3162irgzr.glb",
      "model_3d_step": "dac3162irgzr-etched.step",
      "model_3d_step_plain": "dac3162irgzr.step",
      "lbr": "dac3162irgzr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2680064",
      "digikey": "DAC3162IRGZR-ND",
      "mouser": "595-DAC3162IRGZR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T03:40:38Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "DAC3162IRGZR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-DAC3162IRGZR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "DACCLKP",
        "type": "input",
        "description": "Positive external LVPECL clock input with a self-bias of approximately CLKVDD18/2; data is latched on both edges (DDR), and the clock should be AC coupled."
      },
      {
        "number": "2",
        "name": "DACCLKN",
        "type": "input",
        "description": "Complementary external LVPECL clock input to DACCLKP, which should also be AC coupled."
      },
      {
        "number": "3",
        "name": "D11P",
        "type": "input",
        "description": "LVDS positive-input data bit 11 (MSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "4",
        "name": "D11N",
        "type": "input",
        "description": "LVDS negative-input data bit 11 (MSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "5",
        "name": "D10P",
        "type": "input",
        "description": "LVDS positive-input data bit 10 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "6",
        "name": "D10N",
        "type": "input",
        "description": "LVDS negative-input data bit 10 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "7",
        "name": "D9P",
        "type": "input",
        "description": "LVDS positive-input data bit 9 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "8",
        "name": "D9N",
        "type": "input",
        "description": "LVDS negative-input data bit 9 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "9",
        "name": "D8P",
        "type": "input",
        "description": "LVDS positive-input data bit 8 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "10",
        "name": "D8N",
        "type": "input",
        "description": "LVDS negative-input data bit 8 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "11",
        "name": "D7P",
        "type": "input",
        "description": "LVDS positive-input data bit 7 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "12",
        "name": "D7N",
        "type": "input",
        "description": "LVDS negative-input data bit 7 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "13",
        "name": "D6P",
        "type": "input",
        "description": "LVDS positive-input data bit 6 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "14",
        "name": "D6N",
        "type": "input",
        "description": "LVDS negative-input data bit 6 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "15",
        "name": "DVDD18",
        "type": "power_in",
        "description": "Digital supply voltage of 1.8 V; this supply can be shared with CLKVDD18."
      },
      {
        "number": "16",
        "name": "D5P",
        "type": "input",
        "description": "LVDS positive-input data bit 5 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "17",
        "name": "D5N",
        "type": "input",
        "description": "LVDS negative-input data bit 5 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "18",
        "name": "VREF",
        "type": "power_in",
        "description": "Factory use only; connect to a 0.1-µF decoupling capacitor to GND."
      },
      {
        "number": "19",
        "name": "D4P",
        "type": "input",
        "description": "LVDS positive-input data bit 4 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "20",
        "name": "D4N",
        "type": "input",
        "description": "LVDS negative-input data bit 4 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "21",
        "name": "D3P",
        "type": "input",
        "description": "LVDS positive-input data bit 3 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "22",
        "name": "D3N",
        "type": "input",
        "description": "LVDS negative-input data bit 3 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "23",
        "name": "D2P",
        "type": "input",
        "description": "LVDS positive-input data bit 2 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "24",
        "name": "D2N",
        "type": "input",
        "description": "LVDS negative-input data bit 2 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "25",
        "name": "D1P",
        "type": "input",
        "description": "LVDS positive-input data bit 1 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "26",
        "name": "D1N",
        "type": "input",
        "description": "LVDS negative-input data bit 1 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "27",
        "name": "D0P",
        "type": "input",
        "description": "LVDS positive-input data bit 0 (LSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "28",
        "name": "D0N",
        "type": "input",
        "description": "LVDS negative-input data bit 0 (LSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair."
      },
      {
        "number": "29",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; leave unconnected for normal operation."
      },
      {
        "number": "30",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; leave unconnected for normal operation."
      },
      {
        "number": "31",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; leave unconnected for normal operation."
      },
      {
        "number": "32",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; leave unconnected for normal operation."
      },
      {
        "number": "33",
        "name": "DVDD18",
        "type": "power_in",
        "description": "Digital supply voltage of 1.8 V; this supply can be shared with CLKVDD18."
      },
      {
        "number": "34",
        "name": "SLEEPB",
        "type": "input",
        "description": "Connect to GND to put the device in sleep mode or to AVDD33 for active mode; internal pullup."
      },
      {
        "number": "35",
        "name": "ATEST",
        "type": "output",
        "description": "Factory use only; leave unconnected for normal operation."
      },
      {
        "number": "36",
        "name": "VFUSE",
        "type": "power_in",
        "description": "Digital supply voltage of 1.8 V, also used for factory fuse programming; connect to DVDD18 pins for normal operation."
      },
      {
        "number": "37",
        "name": "IOUTBP",
        "type": "output",
        "description": "B-channel DAC current output; an offset-binary code of 0x0000 gives full-scale current sink and the least-positive voltage on this pin."
      },
      {
        "number": "38",
        "name": "IOUTBN",
        "type": "output",
        "description": "B-channel DAC complementary current output, which has the opposite behavior of IOUTBP (0x0000 gives 0-mA sink and the most-positive voltage)."
      },
      {
        "number": "39",
        "name": "GND",
        "type": "power_in",
        "description": "Ground for all supplies; pins 39 and 46 and the thermal pad on the bottom of the QFN package are ground."
      },
      {
        "number": "40",
        "name": "AVDD33",
        "type": "power_in",
        "description": "Analog supply voltage of 3.3 V."
      },
      {
        "number": "41",
        "name": "DVDD18",
        "type": "power_in",
        "description": "Digital supply voltage of 1.8 V; this supply can be shared with CLKVDD18."
      },
      {
        "number": "42",
        "name": "BIASJ",
        "type": "output",
        "description": "Full-scale output current bias; for 20-mA full-scale output current, connect a 960-Ω resistor to GND."
      },
      {
        "number": "43",
        "name": "AVDD33",
        "type": "power_in",
        "description": "Analog supply voltage of 3.3 V."
      },
      {
        "number": "44",
        "name": "CLKVDD18",
        "type": "power_in",
        "description": "Internal clock buffer supply voltage of 1.8 V; this supply can be shared with DVDD18."
      },
      {
        "number": "45",
        "name": "AVDD33",
        "type": "power_in",
        "description": "Analog supply voltage of 3.3 V."
      },
      {
        "number": "46",
        "name": "GND",
        "type": "power_in",
        "description": "Ground for all supplies; pins 39 and 46 and the thermal pad on the bottom of the QFN package are ground."
      },
      {
        "number": "47",
        "name": "IOUTAN",
        "type": "output",
        "description": "A-channel DAC complementary current output, which has the opposite behavior of IOUTAP (0x0000 gives 0-mA sink and the most-positive voltage)."
      },
      {
        "number": "48",
        "name": "IOUTAP",
        "type": "output",
        "description": "A-channel DAC current output; an offset-binary code of 0x0000 gives full-scale current sink and the least-positive voltage on this pin."
      },
      {
        "number": "49",
        "name": "GND",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The DAC3162 pin table lists NC as pins 25–32, but pins 25–28 are assigned to data bits D1P/D1N/D0P/D; The datasheet gives only the end-points of the data bus (D11P=3, D11N=4, D0P=27, D0N=28) and the ord; The exposed thermal pad on the bottom of the QFN is ground per the datasheet but has no numbered pin",
          "exposed pad 49 added from the footprint"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0859,
        "at": "2026-10-08T03:40:18"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/dac3162",
        "pages": 32,
        "sha256": "2460c4f229cc130b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 49,
        "described": 49,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "dac3162irgzr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          7.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dac3162irgzr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "72fc6e6a66b5f2a0ff251903ec90b52437cb3f2eb22c520932b99c53420387fe",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}