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DAC3162IRGZR

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Texas Instruments Digital To Analog Converters (DAC), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DAC3162IRGZR

Texas Instruments · Digital To Analog Converters (DAC) · QFN-48-EP(7x7)

DAC3162IRGZR from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DACCLKP input Positive external LVPECL clock input with a self-bias of approximately CLKVDD18/2; data is latched on both edges (DDR), and the clock should be AC coupled.
2 DACCLKN input Complementary external LVPECL clock input to DACCLKP, which should also be AC coupled.
3 D11P input LVDS positive-input data bit 11 (MSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
4 D11N input LVDS negative-input data bit 11 (MSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
5 D10P input LVDS positive-input data bit 10 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
6 D10N input LVDS negative-input data bit 10 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
7 D9P input LVDS positive-input data bit 9 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
8 D9N input LVDS negative-input data bit 9 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
9 D8P input LVDS positive-input data bit 8 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
10 D8N input LVDS negative-input data bit 8 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
11 D7P input LVDS positive-input data bit 7 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
12 D7N input LVDS negative-input data bit 7 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
13 D6P input LVDS positive-input data bit 6 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
14 D6N input LVDS negative-input data bit 6 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
15 DVDD18 power_in Digital supply voltage of 1.8 V; this supply can be shared with CLKVDD18.
16 D5P input LVDS positive-input data bit 5 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
17 D5N input LVDS negative-input data bit 5 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
18 VREF power_in Factory use only; connect to a 0.1-µF decoupling capacitor to GND.
19 D4P input LVDS positive-input data bit 4 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
20 D4N input LVDS negative-input data bit 4 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
21 D3P input LVDS positive-input data bit 3 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
22 D3N input LVDS negative-input data bit 3 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
23 D2P input LVDS positive-input data bit 2 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
24 D2N input LVDS negative-input data bit 2 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
25 D1P input LVDS positive-input data bit 1 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
26 D1N input LVDS negative-input data bit 1 of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
27 D0P input LVDS positive-input data bit 0 (LSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
28 D0N input LVDS negative-input data bit 0 (LSB) of the interleaved DDR data bus, with an internal 100-Ω termination between each positive/negative pair.
29 NC unconnected No connect; leave unconnected for normal operation.
30 NC unconnected No connect; leave unconnected for normal operation.
31 NC unconnected No connect; leave unconnected for normal operation.
32 NC unconnected No connect; leave unconnected for normal operation.
33 DVDD18 power_in Digital supply voltage of 1.8 V; this supply can be shared with CLKVDD18.
34 SLEEPB input Connect to GND to put the device in sleep mode or to AVDD33 for active mode; internal pullup.
35 ATEST output Factory use only; leave unconnected for normal operation.
36 VFUSE power_in Digital supply voltage of 1.8 V, also used for factory fuse programming; connect to DVDD18 pins for normal operation.
37 IOUTBP output B-channel DAC current output; an offset-binary code of 0x0000 gives full-scale current sink and the least-positive voltage on this pin.
38 IOUTBN output B-channel DAC complementary current output, which has the opposite behavior of IOUTBP (0x0000 gives 0-mA sink and the most-positive voltage).
39 GND power_in Ground for all supplies; pins 39 and 46 and the thermal pad on the bottom of the QFN package are ground.
40 AVDD33 power_in Analog supply voltage of 3.3 V.
41 DVDD18 power_in Digital supply voltage of 1.8 V; this supply can be shared with CLKVDD18.
42 BIASJ output Full-scale output current bias; for 20-mA full-scale output current, connect a 960-Ω resistor to GND.
43 AVDD33 power_in Analog supply voltage of 3.3 V.
44 CLKVDD18 power_in Internal clock buffer supply voltage of 1.8 V; this supply can be shared with DVDD18.
45 AVDD33 power_in Analog supply voltage of 3.3 V.
46 GND power_in Ground for all supplies; pins 39 and 46 and the thermal pad on the bottom of the QFN package are ground.
47 IOUTAN output A-channel DAC complementary current output, which has the opposite behavior of IOUTAP (0x0000 gives 0-mA sink and the most-positive voltage).
48 IOUTAP output A-channel DAC current output; an offset-binary code of 0x0000 gives full-scale current sink and the least-positive voltage on this pin.
49 GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-48-EP(7x7)
Category Data Acquisition
Pins 49

CAD (KiCad official)

  • Symbol: DAC3162IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: dac3162irgzr-etched.step / dac3162irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac3162irgzr.step / dac3162irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 2460c4f229cc130b, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF