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DAC3151IRGCR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+102@@ -0,0 +1,102 @@+# DAC3151IRGCR++**Texas Instruments** · Digital To Analog Converters (DAC) · VQFN-64-EP(9x9)++DAC3151IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DACCLKP | input | Positive LVPECL clock input for the DAC core with a self-bias of approximately CLKVDD18 / 2. |+| 2 | DACCLKN | input | Negative LVPECL clock input for the DAC core with a self-bias of approximately CLKVDD18 / 2. |+| 3 | CLKVDD18 | power_in | 1.8 V clock supply. |+| 4 | ALIGNP | input | Positive LVPECL FIFO output synchronization input captured with the rising edge of DACCLKP/DACCLKN, used to reset the clock dividers and for multiple DAC synchronization; can be left unconnected if unused. |+| 5 | ALIGNN | input | Negative LVPECL FIFO output synchronization input captured with the rising edge of DACCLKP/DACCLKN, used to reset the clock dividers and for multiple DAC synchronization; can be left unconnected if unused. |+| 6 | SYNCP | input | Positive LVDS input to reset the FIFO or to be used as a syncing source, captured with the rising edge of DATACLKP/DATACLKN. |+| 7 | SYNCN | input | Negative LVDS input to reset the FIFO or to be used as a syncing source, captured with the rising edge of DATACLKP/DATACLKN. |+| 8 | VFUSE | power_in | 1.8 V digital supply that is also used for factory fuse programming; connect to DVDD pins for normal operation. |+| 9 | D9P | input | LVDS data bit 9 positive (MSB) with internal 100-Ω termination, DDR relative to DATACLK. |+| 10 | D9N | input | LVDS data bit 9 negative (MSB) with internal 100-Ω termination, DDR relative to DATACLK. |+| 11 | D8P | input | LVDS data bit 8 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 12 | D8N | input | LVDS data bit 8 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 13 | D7P | input | LVDS data bit 7 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 14 | D7N | input | LVDS data bit 7 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 15 | D6P | input | LVDS data bit 6 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 16 | D6N | input | LVDS data bit 6 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 17 | D5P | input | LVDS data bit 5 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 18 | D5N | input | LVDS data bit 5 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 19 | D4P | input | LVDS data bit 4 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 20 | D4N | input | LVDS data bit 4 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 21 | DIGVDD18 | power_in | 1.8 V digital supply that also supplies the LVDS receivers. |+| 22 | D3P | input | LVDS data bit 3 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 23 | D3N | input | LVDS data bit 3 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 24 | DATACLKP | input | Positive DDR differential input data clock with edge-to-center nominal timing; channel A on rising edge, channel B on falling edge. |+| 25 | DATACLKN | input | Negative DDR differential input data clock with edge-to-center nominal timing; channel A on rising edge, channel B on falling edge. |+| 26 | D2P | input | LVDS data bit 2 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 27 | D2N | input | LVDS data bit 2 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 28 | DIGVDD18 | power_in | 1.8 V digital supply that also supplies the LVDS receivers. |+| 29 | D1P | input | LVDS data bit 1 positive with internal 100-Ω termination, DDR relative to DATACLK. |+| 30 | D1N | input | LVDS data bit 1 negative with internal 100-Ω termination, DDR relative to DATACLK. |+| 31 | D0P | input | LVDS data bit 0 positive (LSB) with internal 100-Ω termination, DDR relative to DATACLK. |+| 32 | D0N | input | LVDS data bit 0 negative (LSB) with internal 100-Ω termination, DDR relative to DATACLK. |+| 33 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 34 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 35 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 36 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 37 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 38 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 39 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 40 | NC | unconnected | Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power. |+| 41 | RESETB | input | Active-low asynchronous serial interface reset that initializes internal registers on the high-to-low transition, with internal pullup; a reset after every power cycle may be needed to restore SPI defaults. |+| 42 | SDENB | input | Serial data enable with internal pullup. |+| 43 | SCLK | input | Serial interface clock with internal pulldown. |+| 44 | SDIO | bidirectional | Bidirectional serial data in 3-pin mode (default) and input only in 4-pin mode, with internal pulldown. |+| 45 | IOVDD | power_in | Supply voltage for CMOS IOs, 1.8 V to 3.3 V. |+| 46 | SDO | output | Unidirectional serial data output in 4-pin mode, tri-stated in 3-pin mode (default), with internal pulldown. |+| 47 | ALARM | output | CMOS output for ALARM condition. |+| 48 | TXENABLE | input | Active-high transmit enable that must be high for data to reach the DAC; when low the digital logic is forced to all 0 and input data is ignored, with internal pulldown. |+| 49 | SLEEP | input | Active-high input that puts the device in sleep, with internal pulldown. |+| 50 | VDDA18 | power_in | Analog 1.8 V supply. |+| 51 | NC | unconnected | Not used; can be left open or tied to ground. |+| 52 | NC | unconnected | Not used; can be left open or tied to ground. |+| 53 | NC | unconnected | Not used; can be left open or tied to ground. |+| 54 | NC | unconnected | Not used; can be left open or tied to ground. |+| 55 | VDDA33 | power_in | Analog 3.3 V supply. |+| 56 | VDDA33 | power_in | Analog 3.3 V supply. |+| 57 | BIASJ | output | Full-scale output current bias; for 20-mA full-scale output current connect a 960-Ω resistor to GND. |+| 58 | EXTIO | bidirectional | External reference input when the internal reference is disabled; requires a 0.1-µF decoupling capacitor to GND when used as reference output. |+| 59 | VDDA33 | power_in | Analog 3.3 V supply. |+| 60 | IOUTAN | output | Negative A-channel DAC current output; 0xFFFF input gives 0 mA source and the least positive voltage on IOUTAP. |+| 61 | IOUTAP | output | Positive A-channel DAC current output; 0x0000 input gives full-scale current source and the most positive voltage on this pin. |+| 62 | NC | unconnected | Not used; can be left open or tied to ground. |+| 63 | NC | unconnected | Not used; can be left open or tied to ground. |+| 64 | VDDA18 | power_in | Analog 1.8 V supply. |+| 65 | GND | power_in | Ground pad on the backside of the package. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(9x9) |+| Category | Data Acquisition |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `DAC3151IRGCR`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `dac3151irgcr-etched.step` / `dac3151irgcr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac3151irgcr.step` / `dac3151irgcr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac3151) (64 pp, sha256 `b35f107ce06f59e4`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac3151irgcr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac3151irgcr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac3151irgcr.kicad_sym",+ "dac3151irgcr.kicad_mod",+ "dac3151irgcr.glb",+ "dac3151irgcr.step",+ "dac3151irgcr.lbr",+ "docs/hero.png",+ "docs/dac3151irgcr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dac3151irgcr-hero.glb",+ "dac3151irgcr-hero.overlay.json"+ ],+ "component": {+ "mpn": "DAC3151IRGCR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-64-EP(9x9)",+ "pin_count": 65,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac3151",+ "parts": {+ "symbol": "dac3151irgcr.kicad_sym",+ "footprint": "dac3151irgcr.kicad_mod",+ "model_3d": "dac3151irgcr-hero.glb",+ "model_3d_plain": "dac3151irgcr.glb",+ "model_3d_step": "dac3151irgcr-etched.step",+ "model_3d_step_plain": "dac3151irgcr.step",+ "lbr": "dac3151irgcr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2868025",+ "digikey": "DAC3151IRGCR-ND",+ "mouser": "595-DAC3151IRGCR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:20:51Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "DAC3151IRGCR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DAC3151IRGCR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DACCLKP",+ "type": "input",+ "description": "Positive LVPECL clock input for the DAC core with a self-bias of approximately CLKVDD18 / 2."+ },+ {+ "number": "2",+ "name": "DACCLKN",+ "type": "input",+ "description": "Negative LVPECL clock input for the DAC core with a self-bias of approximately CLKVDD18 / 2."+ },+ {+ "number": "3",+ "name": "CLKVDD18",+ "type": "power_in",+ "description": "1.8 V clock supply."+ },+ {+ "number": "4",+ "name": "ALIGNP",+ "type": "input",+ "description": "Positive LVPECL FIFO output synchronization input captured with the rising edge of DACCLKP/DACCLKN, used to reset the clock dividers and for multiple DAC synchronization; can be left unconnected if unused."+ },+ {+ "number": "5",+ "name": "ALIGNN",+ "type": "input",+ "description": "Negative LVPECL FIFO output synchronization input captured with the rising edge of DACCLKP/DACCLKN, used to reset the clock dividers and for multiple DAC synchronization; can be left unconnected if unused."+ },+ {+ "number": "6",+ "name": "SYNCP",+ "type": "input",+ "description": "Positive LVDS input to reset the FIFO or to be used as a syncing source, captured with the rising edge of DATACLKP/DATACLKN."+ },+ {+ "number": "7",+ "name": "SYNCN",+ "type": "input",+ "description": "Negative LVDS input to reset the FIFO or to be used as a syncing source, captured with the rising edge of DATACLKP/DATACLKN."+ },+ {+ "number": "8",+ "name": "VFUSE",+ "type": "power_in",+ "description": "1.8 V digital supply that is also used for factory fuse programming; connect to DVDD pins for normal operation."+ },+ {+ "number": "9",+ "name": "D9P",+ "type": "input",+ "description": "LVDS data bit 9 positive (MSB) with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "10",+ "name": "D9N",+ "type": "input",+ "description": "LVDS data bit 9 negative (MSB) with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "11",+ "name": "D8P",+ "type": "input",+ "description": "LVDS data bit 8 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "12",+ "name": "D8N",+ "type": "input",+ "description": "LVDS data bit 8 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "13",+ "name": "D7P",+ "type": "input",+ "description": "LVDS data bit 7 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "14",+ "name": "D7N",+ "type": "input",+ "description": "LVDS data bit 7 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "15",+ "name": "D6P",+ "type": "input",+ "description": "LVDS data bit 6 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "16",+ "name": "D6N",+ "type": "input",+ "description": "LVDS data bit 6 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "17",+ "name": "D5P",+ "type": "input",+ "description": "LVDS data bit 5 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "18",+ "name": "D5N",+ "type": "input",+ "description": "LVDS data bit 5 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "19",+ "name": "D4P",+ "type": "input",+ "description": "LVDS data bit 4 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "20",+ "name": "D4N",+ "type": "input",+ "description": "LVDS data bit 4 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "21",+ "name": "DIGVDD18",+ "type": "power_in",+ "description": "1.8 V digital supply that also supplies the LVDS receivers."+ },+ {+ "number": "22",+ "name": "D3P",+ "type": "input",+ "description": "LVDS data bit 3 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "23",+ "name": "D3N",+ "type": "input",+ "description": "LVDS data bit 3 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "24",+ "name": "DATACLKP",+ "type": "input",+ "description": "Positive DDR differential input data clock with edge-to-center nominal timing; channel A on rising edge, channel B on falling edge."+ },+ {+ "number": "25",+ "name": "DATACLKN",+ "type": "input",+ "description": "Negative DDR differential input data clock with edge-to-center nominal timing; channel A on rising edge, channel B on falling edge."+ },+ {+ "number": "26",+ "name": "D2P",+ "type": "input",+ "description": "LVDS data bit 2 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "27",+ "name": "D2N",+ "type": "input",+ "description": "LVDS data bit 2 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "28",+ "name": "DIGVDD18",+ "type": "power_in",+ "description": "1.8 V digital supply that also supplies the LVDS receivers."+ },+ {+ "number": "29",+ "name": "D1P",+ "type": "input",+ "description": "LVDS data bit 1 positive with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "30",+ "name": "D1N",+ "type": "input",+ "description": "LVDS data bit 1 negative with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "31",+ "name": "D0P",+ "type": "input",+ "description": "LVDS data bit 0 positive (LSB) with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "32",+ "name": "D0N",+ "type": "input",+ "description": "LVDS data bit 0 negative (LSB) with internal 100-Ω termination, DDR relative to DATACLK."+ },+ {+ "number": "33",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "34",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "35",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "36",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "37",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "38",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "39",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "40",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power."+ },+ {+ "number": "41",+ "name": "RESETB",+ "type": "input",+ "description": "Active-low asynchronous serial interface reset that initializes internal registers on the high-to-low transition, with internal pullup; a reset after every power cycle may be needed to restore SPI defaults."+ },+ {+ "number": "42",+ "name": "SDENB",+ "type": "input",+ "description": "Serial data enable with internal pullup."+ },+ {+ "number": "43",+ "name": "SCLK",+ "type": "input",+ "description": "Serial interface clock with internal pulldown."+ },+ {+ "number": "44",+ "name": "SDIO",+ "type": "bidirectional",+ "description": "Bidirectional serial data in 3-pin mode (default) and input only in 4-pin mode, with internal pulldown."+ },+ {+ "number": "45",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Supply voltage for CMOS IOs, 1.8 V to 3.3 V."+ },+ {+ "number": "46",+ "name": "SDO",+ "type": "output",+ "description": "Unidirectional serial data output in 4-pin mode, tri-stated in 3-pin mode (default), with internal pulldown."+ },+ {+ "number": "47",+ "name": "ALARM",+ "type": "output",+ "description": "CMOS output for ALARM condition."+ },+ {+ "number": "48",+ "name": "TXENABLE",+ "type": "input",+ "description": "Active-high transmit enable that must be high for data to reach the DAC; when low the digital logic is forced to all 0 and input data is ignored, with internal pulldown."+ },+ {+ "number": "49",+ "name": "SLEEP",+ "type": "input",+ "description": "Active-high input that puts the device in sleep, with internal pulldown."+ },+ {+ "number": "50",+ "name": "VDDA18",+ "type": "power_in",+ "description": "Analog 1.8 V supply."+ },+ {+ "number": "51",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground."+ },+ {+ "number": "52",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground."+ },+ {+ "number": "53",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground."+ },+ {+ "number": "54",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground."+ },+ {+ "number": "55",+ "name": "VDDA33",+ "type": "power_in",+ "description": "Analog 3.3 V supply."+ },+ {+ "number": "56",+ "name": "VDDA33",+ "type": "power_in",+ "description": "Analog 3.3 V supply."+ },+ {+ "number": "57",+ "name": "BIASJ",+ "type": "output",+ "description": "Full-scale output current bias; for 20-mA full-scale output current connect a 960-Ω resistor to GND."+ },+ {+ "number": "58",+ "name": "EXTIO",+ "type": "bidirectional",+ "description": "External reference input when the internal reference is disabled; requires a 0.1-µF decoupling capacitor to GND when used as reference output."+ },+ {+ "number": "59",+ "name": "VDDA33",+ "type": "power_in",+ "description": "Analog 3.3 V supply."+ },+ {+ "number": "60",+ "name": "IOUTAN",+ "type": "output",+ "description": "Negative A-channel DAC current output; 0xFFFF input gives 0 mA source and the least positive voltage on IOUTAP."+ },+ {+ "number": "61",+ "name": "IOUTAP",+ "type": "output",+ "description": "Positive A-channel DAC current output; 0x0000 input gives full-scale current source and the most positive voltage on this pin."+ },+ {+ "number": "62",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground."+ },+ {+ "number": "63",+ "name": "NC",+ "type": "unconnected",+ "description": "Not used; can be left open or tied to ground."+ },+ {+ "number": "64",+ "name": "VDDA18",+ "type": "power_in",+ "description": "Analog 1.8 V supply."+ },+ {+ "number": "65",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pad on the backside of the package."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Data pin-to-number mapping for DAC3151 (10-bit) was inferred. The printed DATA[9:0] row lists only 1; The DAC3151 datasheet text labels the MSB as DATA13P/DATA13N and LSB as DATA0P/DATA0N in the data-in; The DAC3151 NC row lists pins 33, 34, 39, 40, 51-54, 62, 63 only. Pins 35-38 are NC per the note 'tu",+ "exposed pad 65 added from the footprint"+ ],+ "pages_sent": 19,+ "cost_usd": 0.1646,+ "at": "2026-10-08T20:20:09"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac3151",+ "pages": 64,+ "sha256": "b35f107ce06f59e4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac3151irgcr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac3151irgcr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "19c6decb3f1c6d1f3fbb6454da245b70913a4a9dbe1fbf8485b49ea90eead560",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}