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DAC3151IRGCR

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Texas Instruments Digital To Analog Converters (DAC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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DAC3151IRGCR

Texas Instruments · Digital To Analog Converters (DAC) · VQFN-64-EP(9x9)

DAC3151IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DACCLKP input Positive LVPECL clock input for the DAC core with a self-bias of approximately CLKVDD18 / 2.
2 DACCLKN input Negative LVPECL clock input for the DAC core with a self-bias of approximately CLKVDD18 / 2.
3 CLKVDD18 power_in 1.8 V clock supply.
4 ALIGNP input Positive LVPECL FIFO output synchronization input captured with the rising edge of DACCLKP/DACCLKN, used to reset the clock dividers and for multiple DAC synchronization; can be left unconnected if unused.
5 ALIGNN input Negative LVPECL FIFO output synchronization input captured with the rising edge of DACCLKP/DACCLKN, used to reset the clock dividers and for multiple DAC synchronization; can be left unconnected if unused.
6 SYNCP input Positive LVDS input to reset the FIFO or to be used as a syncing source, captured with the rising edge of DATACLKP/DATACLKN.
7 SYNCN input Negative LVDS input to reset the FIFO or to be used as a syncing source, captured with the rising edge of DATACLKP/DATACLKN.
8 VFUSE power_in 1.8 V digital supply that is also used for factory fuse programming; connect to DVDD pins for normal operation.
9 D9P input LVDS data bit 9 positive (MSB) with internal 100-Ω termination, DDR relative to DATACLK.
10 D9N input LVDS data bit 9 negative (MSB) with internal 100-Ω termination, DDR relative to DATACLK.
11 D8P input LVDS data bit 8 positive with internal 100-Ω termination, DDR relative to DATACLK.
12 D8N input LVDS data bit 8 negative with internal 100-Ω termination, DDR relative to DATACLK.
13 D7P input LVDS data bit 7 positive with internal 100-Ω termination, DDR relative to DATACLK.
14 D7N input LVDS data bit 7 negative with internal 100-Ω termination, DDR relative to DATACLK.
15 D6P input LVDS data bit 6 positive with internal 100-Ω termination, DDR relative to DATACLK.
16 D6N input LVDS data bit 6 negative with internal 100-Ω termination, DDR relative to DATACLK.
17 D5P input LVDS data bit 5 positive with internal 100-Ω termination, DDR relative to DATACLK.
18 D5N input LVDS data bit 5 negative with internal 100-Ω termination, DDR relative to DATACLK.
19 D4P input LVDS data bit 4 positive with internal 100-Ω termination, DDR relative to DATACLK.
20 D4N input LVDS data bit 4 negative with internal 100-Ω termination, DDR relative to DATACLK.
21 DIGVDD18 power_in 1.8 V digital supply that also supplies the LVDS receivers.
22 D3P input LVDS data bit 3 positive with internal 100-Ω termination, DDR relative to DATACLK.
23 D3N input LVDS data bit 3 negative with internal 100-Ω termination, DDR relative to DATACLK.
24 DATACLKP input Positive DDR differential input data clock with edge-to-center nominal timing; channel A on rising edge, channel B on falling edge.
25 DATACLKN input Negative DDR differential input data clock with edge-to-center nominal timing; channel A on rising edge, channel B on falling edge.
26 D2P input LVDS data bit 2 positive with internal 100-Ω termination, DDR relative to DATACLK.
27 D2N input LVDS data bit 2 negative with internal 100-Ω termination, DDR relative to DATACLK.
28 DIGVDD18 power_in 1.8 V digital supply that also supplies the LVDS receivers.
29 D1P input LVDS data bit 1 positive with internal 100-Ω termination, DDR relative to DATACLK.
30 D1N input LVDS data bit 1 negative with internal 100-Ω termination, DDR relative to DATACLK.
31 D0P input LVDS data bit 0 positive (LSB) with internal 100-Ω termination, DDR relative to DATACLK.
32 D0N input LVDS data bit 0 negative (LSB) with internal 100-Ω termination, DDR relative to DATACLK.
33 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
34 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
35 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
36 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
37 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
38 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
39 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
40 NC unconnected Not used; can be left open or tied to ground, and TI recommends turning off pins 33-40 (register lvdsdata_ena) to save power.
41 RESETB input Active-low asynchronous serial interface reset that initializes internal registers on the high-to-low transition, with internal pullup; a reset after every power cycle may be needed to restore SPI defaults.
42 SDENB input Serial data enable with internal pullup.
43 SCLK input Serial interface clock with internal pulldown.
44 SDIO bidirectional Bidirectional serial data in 3-pin mode (default) and input only in 4-pin mode, with internal pulldown.
45 IOVDD power_in Supply voltage for CMOS IOs, 1.8 V to 3.3 V.
46 SDO output Unidirectional serial data output in 4-pin mode, tri-stated in 3-pin mode (default), with internal pulldown.
47 ALARM output CMOS output for ALARM condition.
48 TXENABLE input Active-high transmit enable that must be high for data to reach the DAC; when low the digital logic is forced to all 0 and input data is ignored, with internal pulldown.
49 SLEEP input Active-high input that puts the device in sleep, with internal pulldown.
50 VDDA18 power_in Analog 1.8 V supply.
51 NC unconnected Not used; can be left open or tied to ground.
52 NC unconnected Not used; can be left open or tied to ground.
53 NC unconnected Not used; can be left open or tied to ground.
54 NC unconnected Not used; can be left open or tied to ground.
55 VDDA33 power_in Analog 3.3 V supply.
56 VDDA33 power_in Analog 3.3 V supply.
57 BIASJ output Full-scale output current bias; for 20-mA full-scale output current connect a 960-Ω resistor to GND.
58 EXTIO bidirectional External reference input when the internal reference is disabled; requires a 0.1-µF decoupling capacitor to GND when used as reference output.
59 VDDA33 power_in Analog 3.3 V supply.
60 IOUTAN output Negative A-channel DAC current output; 0xFFFF input gives 0 mA source and the least positive voltage on IOUTAP.
61 IOUTAP output Positive A-channel DAC current output; 0x0000 input gives full-scale current source and the most positive voltage on this pin.
62 NC unconnected Not used; can be left open or tied to ground.
63 NC unconnected Not used; can be left open or tied to ground.
64 VDDA18 power_in Analog 1.8 V supply.
65 GND power_in Ground pad on the backside of the package.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Data Acquisition
Pins 65

CAD (KiCad official)

  • Symbol: DAC3151IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: dac3151irgcr-etched.step / dac3151irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac3151irgcr.step / dac3151irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 b35f107ce06f59e4, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF