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DAC128S085CIMTX

Public Made by Adom

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Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs dac128s085cimtx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
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dac128s085cimtx-etched.glb dac128s085cimtx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
dac128s085cimtx-etched.step dac128s085cimtx: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
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package.json dac128s085cimtx: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
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DAC128S085CIMTX

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16

DAC128S085CIMTX from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
2 DOUT output Serial Data Output utilized in daisy chain operation. Data is not available at DOUT unless SYNC remains low for more than 16 SCLK cycles.
3 VOUTA output Channel A Analog Output Voltage with output range 0 V to VREF1.
4 VOUTB output Channel B Analog Output Voltage with output range 0 V to VREF1.
5 VOUTC output Channel C Analog Output Voltage with output range 0 V to VREF1.
6 VOUTD output Channel D Analog Output Voltage with output range 0 V to VREF1.
7 VA power_in Power supply input with voltage range 2.7 V to 5.5 V. Must be decoupled to GND.
8 VREF1 input Unbuffered reference voltage shared by Channels A, B, C, and D with input voltage range 0.5 V to VA. Must be decoupled to GND.
9 VREF2 input Unbuffered reference voltage shared by Channels E, F, G, and H with input voltage range 0.5 V to VA. Must be decoupled to GND.
10 GND power_in Ground reference for all on-chip circuitry.
11 VOUTH output Channel H Analog Output Voltage with output range 0 V to VREF2.
12 VOUTG output Channel G Analog Output Voltage with output range 0 V to VREF2.
13 VOUTF output Channel F Analog Output Voltage with output range 0 V to VREF2.
14 VOUTE output Channel E Analog Output Voltage with output range 0 V to VREF2.
15 SYNC input Frame Synchronization Input. When low, data is written into the DAC's input shift register on the falling edges of SCLK. A rising edge after the 16th falling edge of SCLK causes the DAC to be updated.
16 SCLK input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin with maximum frequency 40 MHz.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Acquisition
Pins 16

CAD (KiCad official)

  • Symbol: DAC128S085CIMTX
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: dac128s085cimtx-etched.step / dac128s085cimtx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac128s085cimtx.step / dac128s085cimtx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 12de1f4c3c2baa00, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF