component
DAC128S085CIMTX
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# DAC128S085CIMTX++**Texas Instruments** · Digital To Analog Converters (DAC) · TSSOP-16++DAC128S085CIMTX from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DIN | input | Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. |+| 2 | DOUT | output | Serial Data Output utilized in daisy chain operation. Data is not available at DOUT unless SYNC remains low for more than 16 SCLK cycles. |+| 3 | VOUTA | output | Channel A Analog Output Voltage with output range 0 V to VREF1. |+| 4 | VOUTB | output | Channel B Analog Output Voltage with output range 0 V to VREF1. |+| 5 | VOUTC | output | Channel C Analog Output Voltage with output range 0 V to VREF1. |+| 6 | VOUTD | output | Channel D Analog Output Voltage with output range 0 V to VREF1. |+| 7 | VA | power_in | Power supply input with voltage range 2.7 V to 5.5 V. Must be decoupled to GND. |+| 8 | VREF1 | input | Unbuffered reference voltage shared by Channels A, B, C, and D with input voltage range 0.5 V to VA. Must be decoupled to GND. |+| 9 | VREF2 | input | Unbuffered reference voltage shared by Channels E, F, G, and H with input voltage range 0.5 V to VA. Must be decoupled to GND. |+| 10 | GND | power_in | Ground reference for all on-chip circuitry. |+| 11 | VOUTH | output | Channel H Analog Output Voltage with output range 0 V to VREF2. |+| 12 | VOUTG | output | Channel G Analog Output Voltage with output range 0 V to VREF2. |+| 13 | VOUTF | output | Channel F Analog Output Voltage with output range 0 V to VREF2. |+| 14 | VOUTE | output | Channel E Analog Output Voltage with output range 0 V to VREF2. |+| 15 | SYNC | input | Frame Synchronization Input. When low, data is written into the DAC's input shift register on the falling edges of SCLK. A rising edge after the 16th falling edge of SCLK causes the DAC to be updated. |+| 16 | SCLK | input | Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin with maximum frequency 40 MHz. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `DAC128S085CIMTX`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `dac128s085cimtx-etched.step` / `dac128s085cimtx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac128s085cimtx.step` / `dac128s085cimtx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac128s085) (38 pp, sha256 `12de1f4c3c2baa00`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac128s085cimtx-datasheet.pdf)
page.jsonadded+189@@ -0,0 +1,189 @@+{+ "slug": "dac128s085cimtx",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "dac128s085cimtx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dac128s085cimtx.kicad_sym",+ "dac128s085cimtx.kicad_mod",+ "dac128s085cimtx.glb",+ "dac128s085cimtx.step",+ "dac128s085cimtx.lbr",+ "docs/hero.png",+ "docs/dac128s085cimtx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DAC128S085CIMTX",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Data Acquisition",+ "subcategory": "Digital To Analog Converters (DAC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dac128s085",+ "parts": {+ "symbol": "dac128s085cimtx.kicad_sym",+ "footprint": "dac128s085cimtx.kicad_mod",+ "model_3d": "dac128s085cimtx-etched.glb",+ "model_3d_plain": "dac128s085cimtx.glb",+ "model_3d_step": "dac128s085cimtx-etched.step",+ "model_3d_step_plain": "dac128s085cimtx.step",+ "lbr": "dac128s085cimtx.lbr"+ },+ "distributor_links": {+ "lcsc": "C882851"+ },+ "pins": [+ {+ "number": "1",+ "name": "DIN",+ "type": "input",+ "description": "Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC."+ },+ {+ "number": "2",+ "name": "DOUT",+ "type": "output",+ "description": "Serial Data Output utilized in daisy chain operation. Data is not available at DOUT unless SYNC remains low for more than 16 SCLK cycles."+ },+ {+ "number": "3",+ "name": "VOUTA",+ "type": "output",+ "description": "Channel A Analog Output Voltage with output range 0 V to VREF1."+ },+ {+ "number": "4",+ "name": "VOUTB",+ "type": "output",+ "description": "Channel B Analog Output Voltage with output range 0 V to VREF1."+ },+ {+ "number": "5",+ "name": "VOUTC",+ "type": "output",+ "description": "Channel C Analog Output Voltage with output range 0 V to VREF1."+ },+ {+ "number": "6",+ "name": "VOUTD",+ "type": "output",+ "description": "Channel D Analog Output Voltage with output range 0 V to VREF1."+ },+ {+ "number": "7",+ "name": "VA",+ "type": "power_in",+ "description": "Power supply input with voltage range 2.7 V to 5.5 V. Must be decoupled to GND."+ },+ {+ "number": "8",+ "name": "VREF1",+ "type": "input",+ "description": "Unbuffered reference voltage shared by Channels A, B, C, and D with input voltage range 0.5 V to VA. Must be decoupled to GND."+ },+ {+ "number": "9",+ "name": "VREF2",+ "type": "input",+ "description": "Unbuffered reference voltage shared by Channels E, F, G, and H with input voltage range 0.5 V to VA. Must be decoupled to GND."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for all on-chip circuitry."+ },+ {+ "number": "11",+ "name": "VOUTH",+ "type": "output",+ "description": "Channel H Analog Output Voltage with output range 0 V to VREF2."+ },+ {+ "number": "12",+ "name": "VOUTG",+ "type": "output",+ "description": "Channel G Analog Output Voltage with output range 0 V to VREF2."+ },+ {+ "number": "13",+ "name": "VOUTF",+ "type": "output",+ "description": "Channel F Analog Output Voltage with output range 0 V to VREF2."+ },+ {+ "number": "14",+ "name": "VOUTE",+ "type": "output",+ "description": "Channel E Analog Output Voltage with output range 0 V to VREF2."+ },+ {+ "number": "15",+ "name": "SYNC",+ "type": "input",+ "description": "Frame Synchronization Input. When low, data is written into the DAC's input shift register on the falling edges of SCLK. A rising edge after the 16th falling edge of SCLK causes the DAC to be updated."+ },+ {+ "number": "16",+ "name": "SCLK",+ "type": "input",+ "description": "Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin with maximum frequency 40 MHz."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 38,+ "cost_usd": 0.3369,+ "at": "2026-09-23T07:12:28"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac128s085",+ "pages": 38,+ "sha256": "12de1f4c3c2baa00",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}