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DAC124S085CISD

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Texas Instruments Digital To Analog Converters (DACs), WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiondac124s085cisdfactory-2.0.0extractor-text

Verified DAC124S085CISD

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 11 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC124S085CISD · WSON-10-EP(3x3) · 11 pins
  • ✓copper: 11 copper pads, none touching another net
  • ✓datasheet: all 11 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C2864210, digikey DAC124S085CISDTR-ND, mouser 926-DAC124S085CISD
  • ✓family: VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-x4ah7egm/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 11 pins = 11 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 11 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac124s085cisd.kicad_sym✓ dac124s085cisd.kicad_mod✓ dac124s085cisd.step
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Ray Publish 0.1.0 31df5f8 7d ago

DAC124S085CISD

Texas Instruments · Digital To Analog Converters (DACs) · WSON-10-EP(3x3)

DAC124S085CISD from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VA power_in Power supply input, 2.7 V to 5.5 V, must be decoupled to GND.
2 VOUTA output Channel A analog output voltage.
3 VOUTB output Channel B analog output voltage.
4 VOUTC output Channel C analog output voltage.
5 VOUTD output Channel D analog output voltage.
6 GND power_in Ground reference for all on-chip circuitry.
7 VREFIN input Unbuffered reference voltage shared by all channels, 1 V to VA, must be decoupled to GND.
8 DIN input Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
9 SYNC input Frame synchronization input; when low it enables the input shift register, the DAC updates on the 16th clock cycle, and a SYNC rising edge before the 16th clock causes the write to be ignored.
10 SCLK input Serial clock input up to 40 MHz; data is clocked into the input shift register on the falling edges of this pin.
11 PAD passive Exposed die attach pad (WSON only) that can be connected to ground or left floating; soldering it to the PCB gives optimal thermal performance and package self-alignment.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-10-EP(3x3)
Category ADC/DAC/Data Conversion
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VA 6.5 V 4
Voltage on any input pin -0.3 6.5 V 4
Input current at any pin 10 mA 4
Package input current 20 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD HBM V(ESD) -2500 2500 V Human-body model (HBM) 4
ESD MM V(ESD) -250 250 V Machine model (MM) 4
Supply voltage VA 2.7 5.5 V 4
Reference voltage VREFIN 1 V max is VA 4
Digital input voltage 0 5.5 V 4
Output load 0 1500 pF 4
SCLK frequency 40 MHz 4
Operating temperature TA -40 105 °C 4
Junction-to-ambient thermal resistance RθJA 250 °C/W DSC (WSON) 5
Junction-to-case (top) thermal resistance RθJC(top) 40.7 °C/W DSC (WSON) 5
Junction-to-board thermal resistance RθJB 23.7 °C/W DSC (WSON) 5
Junction-to-top characterization parameter ψJT 0.4 °C/W DSC (WSON) 5
Junction-to-board characterization parameter ψJB 23.8 °C/W DSC (WSON) 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 4.7 °C/W DSC (WSON) 5
Resolution 12 Bits -40°C ≤ TA ≤ 105°C 5
Monotonicity 12 Bits -40°C ≤ TA ≤ 105°C 5
Integral non-linearity INL -8 8 LSB -40°C ≤ TA ≤ 105°C 5
Integral non-linearity INL 2.4 LSB TA = 25°C (typ ±2.4) 5
Differential non-linearity DNL -0.5 0.7 LSB VA = 2.7 V to 5.5 V, -40°C ≤ TA ≤ 105°C 5
Differential non-linearity DNL -0.5 0.5 LSB VA = 4.5 V to 5.5 V, -40°C ≤ TA ≤ 105°C 5
Zero code error ZE 15 mV IOUT = 0 mA, -40°C ≤ TA ≤ 105°C 5
Full-scale error FSE -0.75 %FSR IOUT = 0 mA, -40°C ≤ TA ≤ 105°C 5
Gain error GE -1 %FSR All ones loaded to DAC register, -40°C ≤ TA ≤ 105°C 5
Output voltage range 0 V -40°C ≤ TA ≤ 105°C, up to VREFIN 5
High-impedance output leakage current IOZ -1 1 µA -40°C ≤ TA ≤ 105°C 5
Zero code output ZCO 6 mV VA = 3 V, IOUT = 1 mA 5
Full-scale output FSO 2.934 V VA = 3 V, IOUT = 1 mA 5
Input range minimum VREFIN 1 V -40°C ≤ TA ≤ 105°C 6
Input current IIN -1 1 µA -40°C ≤ TA ≤ 105°C 6
Input low voltage VIL 0.6 V VA = 3 V, -40°C ≤ TA ≤ 105°C 6
Input low voltage VIL 0.8 V VA = 5 V, -40°C ≤ TA ≤ 105°C 6
Input high voltage VIH 2.1 V VA = 3 V, -40°C ≤ TA ≤ 105°C 6
Input high voltage VIH 2.4 V VA = 5 V, -40°C ≤ TA ≤ 105°C 6
Input capacitance CIN 3 pF -40°C ≤ TA ≤ 105°C 6
Supply voltage minimum VA 2.7 V -40°C ≤ TA ≤ 105°C 6
Supply voltage maximum VA 5.5 V -40°C ≤ TA ≤ 105°C 6
Normal supply current IN 485 µA fSCLK = 30 MHz, output unloaded, VA = 2.7 V to 3.6 V, -40°C ≤ TA ≤ 105°C 6
Normal supply current IN 650 µA fSCLK = 30 MHz, output unloaded, VA = 4.5 V to 5.5 V, -40°C ≤ TA ≤ 105°C 6
Power-down supply current IPD 1 µA All PD modes, VA = 2.7 V to 3.6 V, -40°C ≤ TA ≤ 105°C 6
Normal supply power PN 1.7 mW fSCLK = 30 MHz, output unloaded, VA = 2.7 V to 3.6 V, -40°C ≤ TA ≤ 105°C 7
Normal supply power PN 3.6 mW fSCLK = 30 MHz, output unloaded, VA = 4.5 V to 5.5 V, -40°C ≤ TA ≤ 105°C 7
Power-down supply power PPD 0.3 3.6 µW All PD modes, VA = 2.7 V to 3.6 V 7
Power-down supply power PPD 0.8 5.5 µW All PD modes, VA = 4.5 V to 5.5 V 7
SCLK frequency fSCLK 30 MHz -40°C ≤ TA ≤ 105°C 7
Output voltage settling time ts 8.5 µs 400h to C00h code change, RL = 2 kΩ, CL = 200 pF, -40°C ≤ TA ≤ 105°C 7
SCLK cycle time 1/fSCLK 33 ns -40°C ≤ TA ≤ 105°C 7
SCLK high time tCH 10 ns -40°C ≤ TA ≤ 105°C 7
SCLK low time tCL 10 ns -40°C ≤ TA ≤ 105°C 7
SYNC set-up time prior to SCLK falling edge tSS 10 ns -40°C ≤ TA ≤ 105°C 7
Data set-up time prior to SCLK falling edge tDS 3.5 ns -40°C ≤ TA ≤ 105°C 7
Data hold time after SCLK falling edge tDH 3.5 ns -40°C ≤ TA ≤ 105°C 7
SCLK fall prior to rise of SYNC tCFSR 3 ns -40°C ≤ TA ≤ 105°C 7
SYNC high time tSYNC 10 ns -40°C ≤ TA ≤ 105°C 8
Zero code error drift ZCED -20 µV/°C 5
Gain error tempco TC GE -1 ppm/°C VA = 5 V 5

CAD (KiCad official)

  • Symbol: DAC124S085CISD
  • Footprint: Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm
  • 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: dac124s085cisd-etched.step / dac124s085cisd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac124s085cisd.step / dac124s085cisd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 5f285252a1a8ac00, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF