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DAC104S085QIMMX

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Texas Instruments Digital To Analog Converters (DACs), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiondac104s085qimmxfactory-2.0.0extractor-text

Verified DAC104S085QIMMX

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC104S085QIMMX · VSSOP-10-0.5mm · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 34-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-bcls97u1/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac104s085qimmx.kicad_sym✓ dac104s085qimmx.kicad_mod✓ dac104s085qimmx.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

DAC104S085QIMMX

Texas Instruments · Digital To Analog Converters (DACs) · VSSOP-10-0.5mm

DAC104S085QIMMX from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VA power_in Power supply input that must be decoupled to GND.
2 VOUTA output Analog output voltage of DAC channel A.
3 VOUTB output Analog output voltage of DAC channel B.
4 VOUTC output Analog output voltage of DAC channel C.
5 VOUTD output Analog output voltage of DAC channel D.
6 GND power_in Ground reference for all on-chip circuitry.
7 VREFIN input Unbuffered reference voltage shared by all channels that must be decoupled to GND.
8 DIN input Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
9 SYNC input Frame synchronization input that enables the input shift register when low; a rising edge before the 16th clock cycle aborts the write sequence, and the DAC updates on the 16th clock cycle otherwise.
10 SCLK input Serial clock input; data is clocked into the input shift register on its falling edges.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-10-0.5mm
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VA 6.5 V 4
Voltage on any input pin -0.3 6.5 V 4
Input current at any pin 10 mA 4
Package input current 20 mA 4
Junction temperature 150 °C 4
Storage temperature Tstg -65 150 °C 4
Operating temperature -40 125 °C 4
Supply voltage VA 2.7 5.5 V 4
Reference voltage VREFIN 1 V maximum is VA 4
Digital input voltage 0 5.5 V 4
Output load 0 1500 pF 4
SCLK frequency fSCLK 40 MHz 5
Integral non-linearity INL -2 2 LSB TMIN ≤ TA ≤ TMAX 5
Differential non-linearity DNL -0.25 0.35 LSB VA = 2.7 V to 5.5 V, TMIN ≤ TA ≤ TMAX 5
Zero code error ZE 15 mV IOUT = 0 mA, TMIN ≤ TA ≤ TMAX 5
Full-scale error FSE -0.75 %FSR IOUT = 0 mA, TMIN ≤ TA ≤ TMAX 5
Gain error GE -1 %FSR All ones Loaded to DAC register, TMIN ≤ TA ≤ TMAX 5
Output voltage range minimum 0 V upper limit VREFIN, TMIN ≤ TA ≤ TMAX 5
High-impedance output leakage current IOZ -1 1 µA TMIN ≤ TA ≤ TMAX 5
Continuous output current IO 11 mA Available on each DAC output, TMIN ≤ TA ≤ TMAX 6
Maximum load capacitance CL 1500 pF RL = ∞ 6
Reference input range minimum VREFIN 1 V TMIN ≤ TA ≤ TMAX 6
Input current IIN -1 1 µA TMIN ≤ TA ≤ TMAX 6
Input low voltage VIL 0.6 V VA = 3 V, TMIN ≤ TA ≤ TMAX 6
Input low voltage VIL 0.8 V VA = 5 V, TMIN ≤ TA ≤ TMAX 6
Input high voltage VIH 2.1 V VA = 3 V, TMIN ≤ TA ≤ TMAX 6
Input high voltage VIH 2.4 V VA = 5 V, TMIN ≤ TA ≤ TMAX 6
Normal supply current IN 485 µA fSCLK = 30 MHz, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX 6
Normal supply current IN 650 µA fSCLK = 30 MHz, VA = 4.5 V to 5.5 V, TMIN ≤ TA ≤ TMAX 6
Power-down supply current IPD 1 µA All PD Modes, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX 6
Normal supply power PN 1.7 mW fSCLK = 30 MHz, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX 7
Normal supply power PN 3.6 mW fSCLK = 30 MHz, VA = 4.5 V to 5.5 V, TMIN ≤ TA ≤ TMAX 7
Power-down supply power PPD 3.6 µW All PD Modes, VA = 2.7 V to 3.6 V, TMIN ≤ TA ≤ TMAX 7
Power-down supply power PPD 5.5 µW All PD Modes, VA = 4.5 V to 5.5 V, TMIN ≤ TA ≤ TMAX 7
SCLK frequency fSCLK 30 MHz TMIN ≤ TA ≤ TMAX 7
Output voltage settling time ts 6 µs 100h to 300h code change, RL = 2 kΩ, CL = 200 pF, TMIN ≤ TA ≤ TMAX 7
SCLK cycle time 1/fSCLK 33 ns TMIN ≤ TA ≤ TMAX 7
SCLK high time tCH 10 ns TMIN ≤ TA ≤ TMAX 7
SCLK low time tCL 10 ns TMIN ≤ TA ≤ TMAX 7
SYNC set-up time prior to SCLK falling edge tSS 10 ns TMIN ≤ TA ≤ TMAX 7
Data set-up time prior to SCLK falling edge tDS 3.5 ns TMIN ≤ TA ≤ TMAX 7
Data hold time after SCLK falling edge tDH 3.5 ns TMIN ≤ TA ≤ TMAX 7
SCLK fall prior to rise of SYNC tCFSR 3 ns TMIN ≤ TA ≤ TMAX 7
SYNC high time tSYNC 10 ns TMIN ≤ TA ≤ TMAX 8
Zero code error drift ZCED -20 µV/°C 5
Gain error tempco TC GE -0.7 ppm/°C VA = 3 V 5
Gain error tempco TC GE -1 ppm/°C VA = 5 V 5
DC output impedance ZOUT 7.5 Ω 6
Input impedance 30 kΩ 6
Input capacitance CIN 3 pF TMIN ≤ TA ≤ TMAX 6
Normal supply current IN 350 µA fSCLK = 30 MHz, VA = 2.7 V to 3.6 V 6
Normal supply current IN 500 µA fSCLK = 30 MHz, VA = 4.5 V to 5.5 V 6
Power-down supply current IPD 0.1 µA All PD Modes, VA = 2.7 V to 3.6 V 6
Normal supply power PN 1.1 mW fSCLK = 30 MHz, VA = 2.7 V to 3.6 V 7
Normal supply power PN 2.5 mW fSCLK = 30 MHz, VA = 4.5 V to 5.5 V 7
Power-down supply power PPD 0.3 µW All PD Modes, VA = 2.7 V to 3.6 V 7
Power-down supply power PPD 0.8 µW All PD Modes, VA = 4.5 V to 5.5 V 7
Junction-to-ambient thermal resistance (DGS VSSOP) RθJA 159 °C/W 5

CAD (KiCad official)

  • Symbol: DAC104S085QIMMX
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
  • 3D model files: dac104s085qimmx-etched.step / dac104s085qimmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac104s085qimmx.step / dac104s085qimmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 d5d1572a225917fd, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF