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DAC101S101QCMK

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Texas Instruments Digital To Analog Converters (DACs), TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersdac101s101qcmkfactory-2.0.0extractor-text

Verified DAC101S101QCMK

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 6 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DAC101S101QCMK · TSOT-23-6 · 6 pins
  • ✓copper: 6 copper pads, none touching another net
  • ✓datasheet: all 6 pin names found in the 38-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TSOT-23-6
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-x7vffogy/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.35)
  • ✓pads: 6 pins = 6 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 6 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dac101s101qcmk.kicad_sym✓ dac101s101qcmk.kicad_mod✓ dac101s101qcmk.step
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Ray Publish 0.1.0 1782a12

DAC101S101QCMK

Texas Instruments · Digital To Analog Converters (DACs) · TSOT-23-6

DAC101S101QCMK from Texas Instruments, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output DAC analog output voltage.
2 GND power_in Ground reference for all on-chip circuitry.
3 VA power_in Power supply and reference input (2.7 V to 5.5 V supply range), should be decoupled to GND.
4 DIN input Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
5 SCLK input Serial clock input; data is clocked into the input shift register on the falling edges of this pin.
6 SYNC input Frame synchronization input; when low it enables the input shift register, the DAC updates on the 16th clock cycle unless SYNC is brought high before then, in which case the write is ignored.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSOT-23-6
Category Data Converters
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VA 6.5 V 4
Voltage on any input pin -0.3 V max is VA + 0.3 4
Input current at any pin 10 mA 4
Package input current 20 mA 4
Storage temperature Tstg -65 150 °C 4
ESD HBM V(ESD) -2500 2500 V HBM per AEC Q100-002 4
Supply voltage VA 2.7 5.5 V 5
Operating temperature TA -40 125 °C DAC101S101-Q1 5
Any input voltage -0.1 V max is VA + 0.1 5
Output load 0 1500 pF 5
SCLK frequency fSCLK 30 MHz Up to 5
Integral non-linearity INL -2.8 2.8 LSB Over decimal codes 12 to 1011; -40°C ≤ TA ≤ +125°C 6
Differential non-linearity DNL -0.2 0.35 LSB VA = 2.7 V to 5.5 V; -40°C ≤ TA ≤ +125°C 6
Zero code error ZE 3.3 15 mV IOUT = 0; max over -40°C ≤ TA ≤ +125°C 6
Full-scale error FSE -1 -0.06 %FSR IOUT = 0; limit over -40°C ≤ TA ≤ +125°C 6
Gain error GE -1 -0.1 1 %FSR All ones loaded to DAC register; limits over -40°C ≤ TA ≤ +125°C 6
Zero code error drift ZCED -20 µV/°C 6
Gain error tempco TC GE -0.7 ppm/°C VA = 3 V 6
Gain error tempco TC GE -1 ppm/°C VA = 5 V 6
Output voltage range 0 V max is VA; -40°C ≤ TA ≤ +125°C 6
Maximum load capacitance 1500 pF RL = 2 kΩ 6
DC output impedance 1.3 Ω 6
Output short circuit current IOS -63 mA VA = 5 V, VOUT = 0 V, Input code = 3FFh 6
Input current IIN -1 1 µA -40°C ≤ TA ≤ +125°C 7
Input low voltage VIL 0.8 V VA = 5 V 7
Input low voltage VIL 0.5 V VA = 3 V 7
Input high voltage VIH 2.4 V VA = 5 V 7
Input high voltage VIH 2.1 V VA = 3 V 7
Input capacitance CIN 3 pF -40°C ≤ TA ≤ +125°C 7
Supply current, normal mode IA 256 332 µA fSCLK = 30 MHz, VA = 5.5 V, output unloaded 7
Supply current, normal mode IA 174 226 µA fSCLK = 30 MHz, VA = 3.6 V, output unloaded 7
Supply current, normal mode IA 221 297 µA fSCLK = 20 MHz, VA = 5.5 V, output unloaded 7
Supply current, normal mode IA 154 207 µA fSCLK = 20 MHz, VA = 3.6 V, output unloaded 7
Supply current, power-down IA 0.06 1 µA All PD modes, fSCLK = 0, VA = 5.5 V 7
Supply current, power-down IA 0.04 1 µA All PD modes, fSCLK = 0, VA = 3.6 V 7
Power consumption, normal mode PC 1.41 1.83 mW fSCLK = 30 MHz, VA = 5.5 V 8
Power consumption, normal mode PC 0.63 0.81 mW fSCLK = 30 MHz, VA = 3.6 V 8
Power consumption, power-down PC 0.33 5.5 µW All PD modes, fSCLK = 0, VA = 5.5 V 8
Power consumption, power-down PC 0.14 3.6 µW All PD modes, fSCLK = 0, VA = 3.6 V 8
SCLK frequency fSCLK 30 MHz -40°C ≤ TA ≤ +125°C 9
Output voltage settling time ts 5 7.5 µs 100h to 300h code change, RL = 2 kΩ, CL ≤ 200 pF 9
SCLK cycle time 1/fSCLK 33 ns -40°C ≤ TA ≤ +125°C 9
SCLK high time tH 13 5 ns -40°C ≤ TA ≤ +125°C 9
SCLK low time tL 13 5 ns -40°C ≤ TA ≤ +125°C 9
Set-up time SYNC to SCLK rising edge tSUCL 0 -15 ns -40°C ≤ TA ≤ +125°C 9
Data set-up time tSUD 5 2.5 ns -40°C ≤ TA ≤ +125°C 9
Data hold time tDHD 4.5 2.5 ns -40°C ≤ TA ≤ +125°C 9
SCLK fall to rise of SYNC tCS 3 0 ns VA = 5 V 9
SCLK fall to rise of SYNC tCS 1 -2 ns VA = 3 V 9
SYNC high time tSYNC 20 9 ns 2.7 ≤ VA ≤ 3.6 9
SYNC high time tSYNC 10 5 ns 3.6 ≤ VA ≤ 5.5 9
Output slew rate SR 1 V/µs 9
Wake-up time tWU 6 µs VA = 5 V 9
Wake-up time tWU 39 µs VA = 3 V 9
Junction-to-ambient thermal resistance RθJA 250 °C/W DDC (SOT-23), 6 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 58.8 °C/W DDC (SOT-23), 6 pins 5
Junction-to-board thermal resistance RθJB 30.6 °C/W DDC (SOT-23), 6 pins 5

CAD (KiCad official)

  • Symbol: DAC101S101QCMK
  • Footprint: Package_TO_SOT_SMD:TSOT-23-6
  • 3D model: TSOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: dac101s101qcmk-etched.step / dac101s101qcmk-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dac101s101qcmk.step / dac101s101qcmk.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 1610636f88275605, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF