component
DAC088S085CIMT
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDAC088S085CIMT
Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-16
DAC088S085CIMT from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after SYNC falls. |
| 2 | DOUT | output | Serial data output for daisy-chain operation, connected to DIN of another DAC088S085; data is only available at DOUT if SYNC stays low for more than 16 SCLK cycles. |
| 3 | VOUTA | output | Channel A analog output voltage (rail-to-rail output). |
| 4 | VOUTB | output | Channel B analog output voltage (rail-to-rail output). |
| 5 | VOUTC | output | Channel C analog output voltage (rail-to-rail output). |
| 6 | VOUTD | output | Channel D analog output voltage (rail-to-rail output). |
| 7 | VA | power_in | Power supply input, which must be decoupled to GND; operating range is 2.7 V to 5.5 V. |
| 8 | VREF1 | input | Unbuffered reference voltage shared by channels A, B, C and D; must be decoupled to GND and set between 0.5 V and VA. |
| 9 | VREF2 | input | Unbuffered reference voltage shared by channels E, F, G and H; must be decoupled to GND and set between 0.5 V and VA. |
| 10 | GND | power_in | Ground reference for all on-chip circuitry. |
| 11 | VOUTH | output | Channel H analog output voltage (rail-to-rail output). |
| 12 | VOUTG | output | Channel G analog output voltage (rail-to-rail output). |
| 13 | VOUTF | output | Channel F analog output voltage (rail-to-rail output). |
| 14 | VOUTE | output | Channel E analog output voltage (rail-to-rail output). |
| 15 | SYNC | input | Frame sync input: low enables writes on SCLK falling edges, a rising edge after the 16th SCLK falling edge updates the DAC, and a rising edge before the 15th falling edge aborts the write. |
| 16 | SCLK | input | Serial clock input; data is clocked into the input shift register on its falling edges. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
DAC088S085CIMT - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
dac088s085cimt-etched.step/dac088s085cimt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dac088s085cimt.step/dac088s085cimt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
7daaeb4adb6d55c1, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).