component
DAC0802LCMX
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Texas Instruments Digital To Analog Converters (DAC), SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# DAC0802LCMX++**Texas Instruments** · Digital To Analog Converters (DAC) · SOIC-16++DAC0802LCMX from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | V+ | power_in | Positive supply, operating range (V−)+10 V to (V−)+30 V with absolute maximum supply span (V+ − V−) of ±18 V or 36 V. |+| 2 | VREF(+) | power_in | Non-inverting reference amplifier input; reference input current 1 to 2 mA at V− = −5 V (1 to 4 mA at V− = −15 V), 5 mA absolute maximum, common-mode range V− to V+. |+| 3 | VREF(−) | power_in | Inverting reference amplifier input; reference bias current of −1.0 to −3.0 µA typical-to-max and common-mode range V− to V+. |+| 4 | COMPENSATION | passive | Reference amplifier compensation pin, where a compensation capacitor (CC = 0.01 µF in the typical application) is connected. |+| 5 | THRESHOLD CONTROL, VLC | input | Logic threshold control input that sets VTH = VLC + 1.4 V, grounded (VLC = 0 V) for TTL operation, with threshold range −10 V to 13.5 V. |+| 6 | IOUT (complementary) | output | Complementary current output, where IO + IO-bar = IFS for all logic states, with output voltage compliance −10 V to +18 V. |+| 7 | V− | power_in | Negative supply, operating range −15 V to −5 V, also the reference for logic input limits (V− to V− plus 36 V). |+| 8 | IOUT | output | True current output with full-scale range up to 2.1 mA (V− = −5 V) or 4.2 mA (V− = −8 V to −18 V) and compliance −10 V to +18 V. |+| 9 | B1 (MSB) | input | Digital input bit 1, the most significant bit, with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 10 | B2 | input | Digital input bit 2 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 11 | B3 | input | Digital input bit 3 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 12 | B4 | input | Digital input bit 4 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 13 | B5 | input | Digital input bit 5 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 14 | B6 | input | Digital input bit 6 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 15 | B7 | input | Digital input bit 7 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |+| 16 | B8 (LSB) | input | Digital input bit 8, the least significant bit, with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `DAC0802LCMX`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `dac0802lcmx-etched.step` / `dac0802lcmx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dac0802lcmx.step` / `dac0802lcmx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dac0800) (21 pp, sha256 `18022365c3099e21`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dac0802lcmx-datasheet.pdf)
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reference input current 1 to 2 mA at V− = −5 V (1 to 4 mA at V− = −15 V), 5 mA absolute maximum, common-mode range V− to V+."+ },+ {+ "number": "3",+ "name": "VREF(−)",+ "type": "power_in",+ "description": "Inverting reference amplifier input; reference bias current of −1.0 to −3.0 µA typical-to-max and common-mode range V− to V+."+ },+ {+ "number": "4",+ "name": "COMPENSATION",+ "type": "passive",+ "description": "Reference amplifier compensation pin, where a compensation capacitor (CC = 0.01 µF in the typical application) is connected."+ },+ {+ "number": "5",+ "name": "THRESHOLD CONTROL, VLC",+ "type": "input",+ "description": "Logic threshold control input that sets VTH = VLC + 1.4 V, grounded (VLC = 0 V) for TTL operation, with threshold range −10 V to 13.5 V."+ },+ {+ "number": "6",+ "name": "IOUT (complementary)",+ "type": "output",+ "description": "Complementary current output, where IO + IO-bar = IFS for all logic states, with output voltage compliance −10 V to +18 V."+ },+ {+ "number": "7",+ "name": "V−",+ "type": "power_in",+ "description": "Negative supply, operating range −15 V to −5 V, also the reference for logic input limits (V− to V− plus 36 V)."+ },+ {+ "number": "8",+ "name": "IOUT",+ "type": "output",+ "description": "True current output with full-scale range up to 2.1 mA (V− = −5 V) or 4.2 mA (V− = −8 V to −18 V) and compliance −10 V to +18 V."+ },+ {+ "number": "9",+ "name": "B1 (MSB)",+ "type": "input",+ "description": "Digital input bit 1, the most significant bit, with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "10",+ "name": "B2",+ "type": "input",+ "description": "Digital input bit 2 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "11",+ "name": "B3",+ "type": "input",+ "description": "Digital input bit 3 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "12",+ "name": "B4",+ "type": "input",+ "description": "Digital input bit 4 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "13",+ "name": "B5",+ "type": "input",+ "description": "Digital input bit 5 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "14",+ "name": "B6",+ "type": "input",+ "description": "Digital input bit 6 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "15",+ "name": "B7",+ "type": "input",+ "description": "Digital input bit 7 with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ },+ {+ "number": "16",+ "name": "B8 (LSB)",+ "type": "input",+ "description": "Digital input bit 8, the least significant bit, with logic 0 ≤ 0.8 V and logic 1 ≥ 2.0 V at VLC = 0 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin names for IOUT are rendered with overbars in the figure; the SOIC pin 6 is the complementary (ov; The Figure 3 SOIC pinout is shared by the DAC0800 and DAC0802 families. DAC0802LCMX/NOPB is confirme",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 21,+ "cost_usd": 0.4046,+ "at": "2026-10-08T02:12:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dac0800",+ "pages": 21,+ "sha256": "18022365c3099e21",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dac0802lcmx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dac0802lcmx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8ae88650bcf72c49bbeb7f9e1385294538a17ef75c33e29e36df15bf7b23c0f9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}